純鍺基板是下一代金氧半場效電晶體的前瞻通道材料，但還有許多問題需要克服，例如n型鍺電晶體接面形成不易，以及閘極氧化層介面容易產生較多缺陷……等等。因此如何製作一個穩定的接面以及將閘極氧化層介面鈍化相當重要。本論文研究以高品質遮罩氧化層改善鍺n+/p接面，以及探討HfNx、AlN、GeO2介面層對於n型、p型MOS元件介面的影響，最後製作出n型鍺金氧半場效電晶體，並探討其電特性。
第一部分將介電層二氧化鋯氮化形成氮氧化鋯，探討兩材料對閘極電特性的影響。實驗結果顯示，氮氧化鋯能使電晶體獲得較高的驅動電流，但次臨界擺幅增加。而n+/p接面優化製程，為在離子佈植前利用原子層化學氣相沉積系統(ALD)以電漿形成一層薄二氧化鍺與氧化鋁做為遮罩氧化層，而此氧化層擁有良好的品質也可當作金屬與n+鍺基板邊緣的鈍化層。利用原子層化學氣相沉積系統(ALD)成長一層薄二氧化鍺與沉積氧化鋁做為離子佈植前的遮罩氧化層與表面n+/p接面鈍化層後，得到了很顯著的改善，n+/p接面正偏與逆偏電流比值拉大了105倍。
第二部分在n、p型基板上分別使用不同介面層，搭配Gate first製程的熱預算450℃300秒。從實驗結果可以看出，p型鍺基板應用HfNx作為介面層的元件有良好的變頻電容特性表現，且EOT(0.57nm)也是所有樣品中最小的，甚至連閘極漏電流都是最小的(Vfb-1V時約為5 x10-4A/cm2)。p型基板沒有使用GeO2作為介面層時Dit是比有使用GeO2作為介面層低的，而n型基板有使用GeO2作為介面層時Dit會比沒有使用GeO2作為介面層表現的好。
第三部分應用第二部分的結果以HfNx作為介面層。Source/Drain的形成方式也參照本論文第三章，使用ALD沉積的高品質遮罩氧化層與鈍化層優化PN接面。最後n型電晶體的特性，次臨界擺幅為120mV/dec，在ID-VG轉換特性也表現得不錯，on-off ratio達到2 x103。閘極電容EOT為0.67nm，閘極漏電流在Vfb-1V時為8 x10-4A/cm2，Dit約為4×1012 eV-1cm2。

Germanium (Ge) is regarded as promising channel material for next generation metal oxide semiconductor field effect transistor (MOSFETs). However, there are many challenges for applying Ge as channel material. For example, Ge n+/p junction is hard to be formed, and the interface quality of high-k dielectric is poor. So stable n+/p junction and good passivation of gate dielectric interface are the key technology in Ge nMOSFET. In this thesis, the improved Ge n+/p junction by high quality screen oxide and the effects interfacial layer such as HfNx, AlN, and GeO2 on pGe and nGe MOS device are investigated. Finally, Ge nMOSFETs are fabricated and the electrical characteristic are investigated.
In the first part, effects of ZrO2 and ZrON high-k gate dielectric electrical characteristic of MOSFET are investigated. Sample with ZrON shows higher drive current, but larger subthreshold swing. On the other hand, GeO2 and Al2O3 as high quality screen oxide before implantation were used to improve Ge n+/p junction. Shallow junction and well passivation of metal/n+Ge interface are obtained by this high quality screen oxide. The performance of n+/p junction are significantly improved, and the on-off ratio is increased to 105 times.
In the second part, different interfacial layers are used on pGe and nGe MOS device. With gate first process at 450℃ for 300 sec during PMA. The results show that pGe capacitors with HfNx interface layer have good electrical characteristics, showing the lowest gate leakage current density of 5 x10-4A/cm2 and the smallest 0.57nm EOT. The interface trap density of pGe MOS device w/ GeO2 is higher than that of sample w/o GeO2.The interface trap of nGe MOS w/o GeO2 is higher than that of sample w/ GeO2.
In the third part, HfNx interfacial layer and the source/drain formation as in chapter 3 by using a high quality screen oxide deposited with ALD before implantation were applied to fabricate Ge nMOSFET. Finally, an EOT of 0.67nm, gate leakage current density of 8 x10-4A/cm2, on-off ratio 2 x103 times and subthreshold swing of 120mV/dec are achieved.

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