隨著雲端運算技術的崛起，高速交換網路的需求已變得不可或缺。但由於製程的演進以及線距的縮短，導線之間的串音干擾效應(crosstalk effect)已變得不可忽視，其中我們對於在傳輸中避免出現特定位元樣式(bit patterns)，以達到降低串音干擾的匯流排編碼(bus encoding)感到興趣。

出於對於高速交換網路設計的研究，我們的研究團隊在先前的論文中提出了漸序位元填充演算法(sequential bit stuffing algorithm)。此演算法可以對1組輸入資料位元串流產生禁制躍遷編碼(forbidden transition code)以減輕匯流排中鄰近兩訊號線之間的串音干擾。在這篇論文中，我們更進一步地提出了平行位元填充演算法(parallel bit stuffing algorithm)。平行位元填充演算法可以對一組有n條導線的匯流排且有n組平行輸入資料位元串流產生禁制躍遷編碼，進而減輕匯流排中的串音干擾。本文將介紹平行位元填充演算法理論分析以及實作設計兩部分，同時我們也說明如何將此演算法應用到禁制重疊編碼上(forbidden overlap code)。

在理論方面，藉著馬可夫鏈分析，我們可以證明平行位元填充演算法的編碼率(coding rate)是81.25%，與目前文獻上所能達到最佳的編碼率，也就是漸序位元填充演算法所能達到的82.84%編碼率僅有不到2%的差距。然而，對於實現一組有n條導線的匯流排的平行位元填充演算法的複雜度僅為O(n)，並且於平行位元填充演算法中，我們可以達到n組輸入資料位元串流的編碼器以及解碼器同時平行運作。這也是平行位元填充演算法比起漸序位元填充演算法更可以被規模化(scalable)的原因。

在實做設計中，我們用元件可程式邏輯閘陣列（Field Programmable Gate Array，FPGA）來實現我們的平行位元填充演算法，在我們的設計中，我們不只將匯流排上的資料做禁制躍遷編碼，同時也說明了實作架構中，用簡單的組合邏輯(combinational logic)來產生輸入以及輸出佇列(queue)的控制訊號。

在本文最後，我們說明如何將平行位元填充演算法應用到其禁制重疊編碼，而透過類似的分析及數值運算，我們可以得出使用平行位元填充演算法於禁制重疊編碼的編碼率為95.44%，此編碼率雖比應用在禁制躍遷編碼的編碼率高，但由於限制條件較為寬鬆，因此對於串音干擾的抑制也較為有限。

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