本論文設計一個應用在高速資料傳輸的類比式時脈資料回復電路，並具有1:8解串器將資料做取樣和並行化，供後續系統使用。
這個類比式時脈回復電路主要組成的電路有全速率相位偵測器、頻率偵測器、電荷幫浦、迴路濾波器、壓控振盪器、電壓比較器和模式控制器。在設計上壓控振盪器有16條頻帶可以選擇，頻率可調範圍為15GHz~17.3GHz，操作上，頻率偵測器會先判斷資料傳輸速率位於哪條頻帶內，再由相位偵測器完成時脈鎖定。最後鎖定的時脈經過除頻器產生解串器需要頻率，完成對資料的取樣和產生並行數據。
這個操作在16Gb/s的類比式時脈資料回復電路與解串器使用TSMC 65nm製程設計與驗證，操作電壓1.2V，輸入資料為16Gb/s PRBS31，差動訊號振幅0.6V，還原時脈速率為16GHz，輸出資料速率為2Gb/s，模擬結果時脈峰對峰抖動為3.05ps，輸出資料時脈峰對峰抖動為3.68ps，功耗為82.8mW，電路面積為516.145um×338.795um。

In this paper, an analog clock data recovery circuit is designed for high-speed data transmission, and a 1:8 deserializer is used to sample and parallelize the data for subsequent systems.
The main circuits of this analog clock recovery circuit are full-rate phase detector, frequency detector, charge pump, loop filter, voltage controlled oscillator, voltage comparator, and Mode controller. In the design, the voltage controlled oscillator has 16 frequency bands to choose from, the frequency adjustable range is 15GHz~17.3GHz. In operation, the frequency detector will first determine which frequency band the data transmission rate is in, and then the phase detector completes the clock locking. Finally, the locked clock passes through the divider to generate the frequency required by the deserializer, complete the sampling of the data, and generate parallel data.
This analog clock data recovery circuit and deserializer operating at 16Gb/s is designed and verified using TSMC 65nm process. The operating voltage is 1.2V, the input data is 16Gb/s PRBS31, the differential signal amplitude is 0.6V, the reduction rate is 16GHz, the output data rate is 2Gb/s, the analog results are clock peak-to-peak clock jitter of 3.05ps, the output data peak-to-peak clock jitter of 3.68ps, the power consumption is 82.8mW, and the circuit area is 516.145um×338.795um.

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