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ABSTRACT
The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O leads to rapid expansion in the field of area array packages. In the past few years, the area array package has gained wide acceptance by electronic packaging and surface mount technology (SMT) industries due to its higher processing yield, better thermal/electrical performance and I/O density, etc. Especially on the portable electronic products that low cost, miniaturization, and weight reduction are basic driving factors and tendencies in modern electronics industry. Based on this concept, the growing needs of the present day lead to the evolution of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies which provide lower profiles and better thermal/electrical performance than traditional packages such as SOP, QFP on various consumer applications. In stead of bumping technology and the processing procedures of manufacturing, this research will focus on the reliability analysis of electronic package structures and the solder joint design issues, such as solder geometry shape control, material selection of under bump buffer layer, BCB layer thickness and structural design, etc. In investigating stress and strain of individual component of a typical flip chip / wafer level package due to thermal cycling, this research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition. To complete the analysis and investigation of the reliability issues, FEM parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models. The main goal of this research is to seek an optimized combination of materials to improve reliability of wafer level/flip chip packages. Moreover, this study will extend the developed concept to the wire interconnect technology (WIT) to optimize the structure configuration of the packages such as thickness and materials between die and bump for the reliability considerations. This research will discuss these parameters by adjusting components of the model in the section of the interconnection. To conclude the optimized structure of wafer level and analogous packages, this research will compare the results of FEM models undergo identical loading conditions.

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