研究生: |
陳義忠 Yi-Jhong Chen |
---|---|
論文名稱: |
具有光感測器的液晶顯示面板的數位輸出讀取電路 A digital readout circuit for photo-sensor embedded LCD panel |
指導教授: |
黃惠良
Huey-Liang Hwang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 英文 |
論文頁數: | 59 |
中文關鍵詞: | 光感測電路 、數位類比 、轉換器 |
相關次數: | 點閱:3 下載:0 |
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近年來,平板顯視觸控輸入應用領域,利用非晶矽薄膜電晶體當作光感側元件的應用及發展越來越多元化。於配合主動式液晶顯示器的應用上,通常需要外部多加元件,此如電阻式、電容式 或是電感式的觸控平板元件。這不僅增加元件的材料成本,也相對的影響顯示器的光穿透效率。但若是搭配內建於顯示器的被動式感應電路來使用,則可省去外部多加元件,並可大幅提昇透光度及解析度。此設計為利用平面顯示器前段製程技術,將光感側元件製作在每一個影像畫素中,利用相同於驅動液晶的非晶矽薄膜電晶體,來當感測光信號的元件。此時每一個光信號將可透過光感測電晶體而儲存下來,再經由循序的電路定址,輸出所要的信號,即可達到讀取的功能。
本篇論文裡介紹一種應用在感光式液晶顯示面板的輸出讀取電路,由於感光式的面板是利用光二極體當感應器並且利用光筆當輸入所以容易受背景光源的干擾,故我們希望能把光輸入訊號數位化,藉由數位化後的訊號處理能把訊號跟雜訊兩者分開,本篇論文的重點在於利用極簡單的方法和電路來達成我們要的效果,並利用遲滯型比較器和抗溫度變化的電流鏡來穩定電路並避免雜訊對於電路的甘擾且加入靴帶式升壓電路來提升電路可正常作範圍,此電路優點在於可以縮小電路面積並避免訊號因雜訊干擾而跳動產生的訊號誤判,藉由這樣的讀出電路我們可以對應輸入訊號的軌跡,將輸入的光訊號做正確的讀出。本篇論文的模擬參數是採用 TSMC0352P4M 製程,以HSPICE為模擬軟體。
Recently, for interactive purposes, detecting devices are been developed on the existing TFT-LCD panels. Many of them are based on resistive, capacitive or inductive touch technology. All these solutions require externally added components or one more layer of screen, which add the cost and degrade the optical performance. In our study, we use a novel approach by building an additional TFT photo-diode in the existing LCD display pixel as a detecting element. This diode can be embedded during the panel manufacturing process and incurring no additional cost. After the post-product evaluation, this diode also shows no impediment to the light efficiency. In this way, by using the photo-diode array and by going with a designed detecting circuit, the imaging signal that appears on the panel can then be read out.
In this study we investigate a readout circuit that can be used to distinguish the noise that comes from environment and the signal that comes from our remote controlled light-pen on hand. By the circuit we can get the required results of lower power consumption and smaller integrated chip area in comparison with using conventional ADC. In addition to the advantage of low power supply it has high output voltage swing and is suitable for implementation in advanced submicron CMOS technologies. The circuit proposed above is design in a TSMC 0.35um process and verified by HSPICE program.
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