由於CMOS 製程技術的持續進步，使得電晶體的尺寸持續縮小，然而當電晶體縮小到低於45 nm 以下時，傳統的MOSFET 電晶體會遇到一些問題，例如：汲極與源極之間的次臨界漏電流、閘極漏電流以及製程變異的影響…等等。
因此，作者希望藉由SOI基板及鰭式電晶體的結構來克服上述的因素，鰭式電晶體沒有傳統平面電晶體的上述問題，且鰭式電晶體與傳統平面電晶體的製程差異不大，因此鰭式電晶體被認為是實現VLSI 電路的更好選擇。鰭式電晶體連接汲極與源極之間的通道的形狀像魚鰭一樣，此通道的外型高而薄，而控制通道導通與否的閘極圍住通道的三面，因此閘極對通道有較好的控制性，可以輕易地控制通道是導通或者關閉。
首先，作者成功完成矽在絕緣體上鰭式電晶體之元件，並得到良好的初始特性，Tinv部分可達到1.4 nm，閘極漏電流密度約為2x10-3 A/cm2。電晶體特性方面如汲極電流(3.26x10-5 A/µm)、轉導值(13 µA/V)及載子遷移率(200 cm2/V-sec)皆符合學術界標準，且次臨界擺幅特性很好約為66 mV/dec。
第二部分，為了持續提升元件的特性，作者使用了不同的活化摻雜之方式，試圖使元件之汲極電流、最大轉導值以及界面特性能有進一步改善。實驗結果發現，使用低溫微波退火之元件的Tinv可達1.8 nm以及非常低的閘極漏電流密度6.7 x10-6 A/cm2，而使用雷射後快速熱退火之元件可以得到最大的汲極電流(8.9x10-5 A/μm)、轉導值(24.9 μA/V) 以及載子遷移率(210 cm2/V-s)。在可靠度方面，使用低溫微波退火之元件的特性比使用其他退火方式之元件較佳。
第三部分中，作者在通道高度作調變，並沿用雷射後快速熱退火之方式來活化摻雜，且期望利用雷射後快速退火的方式得到較大的飽和汲極電流並同時能抑制臨界電壓的下降。實驗結果發現，通道高度40nm之元件的次臨界擺幅最低(71 mV/dec)，不同通道高度之元件臨界電壓都可以控制在0.75 V左右，而高度60nm通道之元件會獲得最大之汲極電流(1.3x10-5 A/μm)、轉導值(21 μA/V)以及載子遷移率(220 cm2/V-s)，且在可靠度方面的表現也非常優異。

Transistors’ feature sizes continuingly scale down due to the lasting advancement of CMOS process; nevertheless, conventional MOSFET transistors confront some issues when transistors’ feature sizes scale down lower than 45 nm, such as the effect of subthreshold leakage, gate leakage, process variation, and so on.
Therefore, the author hopes to conquer foregoing factors by SOI substrate and FinFET structure. FinFET doesn’t own the said problems MOSFET transistors have, and the processes of FinFET and MOSFET are less variant. FinFET is thus considered the better choice to attain VLSI circuit.The channel that FinFET connects to drain and sourse looks like fin and its shape is high and thin.The gate which controls path leading or not compasses three sides of channel, hence the gate has the better controlled qulity to make the channel on or off.
First of all, SOI FinFET is successfully finished and gets the good initial qulity. And its Tinv can be scaled down to 1.4 nm, and the gate leakage is reduced to 2x10-3 A/cm2 as well. And the transistor characteristics such as drain current (3.26x10-5 A/μm), transconductance(13 μA/V) and carrier mobility (200 cm2/V-sec) are in compliance with the academic standards, and S.S (Subthreshold Swing) is well about 66 mV/dec.
In the second part, in order to continuously promote device characteristics, the aurthor
uses different doping activation methods to make drain current, Gmmax and interfacial characteristics of device further improved. The experiment results show that the low-temperature-microwave-annealing device gets very low gate leakage current density of 6.7 x10-6 A/cm2 and Tinv can attain to 1.8 nm while the rapid-thermal-annealing-after-laser device can obtain the maximum drain current (8.9x10-5 A/μm), transconductance (24.9 μA/V), and carrier mobility (210 cm2/V-s). And the low-temperature-microwave-annealing device gets the better reliability compared to other annealing devices.
In the third part, the author modulates the channel height, continues using rapid-thermal-annealing-after-laser method to activate the dopant, and anticipates getting the larger drain current and suppress threshold voltage roll-off at the same time by making use of rapid-thermal-annealing-after-laser method. The experiment results show that S.S of the 40nm-channel-height device is the lowest(71 mV/dec). And the threshold voltage of different channel-height devices can all controlled approaching approximately 0.75 V. The 60nm-channel-height device gets maximum drain current (1.3x10-5 A/μm), transconductance (21 μA/V) and carrier mobility (220 cm2/V-s), and the performance of reliability is excellent as well.

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