由於快閃記憶體具備資料可重複地讀寫、長時間之資料保存能力之優點，不僅可使用於程式碼之儲存，近年來已廣泛應用於數位相機、手機及其他個人隨身電子產品之資料儲存媒體。但在現今以省電低耗能的趨勢下，操作電壓也必須隨之降低，因此通常會需要降低元件的穿隧氧化層厚度來降低操作電壓與提升操作速度，但這同時也會影響到元件的特性以及造成可靠度的問題。
在此研究中，我們使用ZnO和NiO堆疊的結構來取代一般記憶體的電荷儲存層。其中ZnO此材料由於傳導帶位置低，可以增加寫入時的穿隧電流以利電子進入儲存層，並且防止儲存的電荷由穿隧氧化層流失，而NiO則提供了許多的缺陷來供電荷儲存。另外，由於ZnO和NiO堆疊會形成一個pn二極體，其二極體的內建電場在寫入時可以防止電子從控制氧化層流向閘極，在抹除時則幫助元件加速電子的排出，以達到小電壓操作。在電性方面，相較於使用單純的ZnO或NiO當電荷儲存層的記憶體，使用ZnO和NiO堆疊形成電荷儲存層的記憶體有著較大的優勢。

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