多電源域MTCMOS設計技術研究｜國立清華大學博碩士論文庫

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳世豪 Chen, Shi-Hao
論文名稱：	多電源域MTCMOS設計技術研究 A Study of Multi-Power Domain MTCMOS Designs
指導教授：	林永隆 Lin, Youn-Long
口試委員:	張世杰黃婷婷蔡仁松王廷基陳宏明趙家佐林景源侯永清林永隆
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	65
中文關鍵詞：	動態電壓降、湧入電流、低功耗設計、多閥值CMOS 、電源門控、啟動順序、斜坡上升時間
外文關鍵詞：	dynamic IR, inrush current, low power design, multi-threshold CMOS (MTCMOS), power gating, power-up sequence, ramp-up time
相關次數：	點閱：4 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

電源門控能有夠效地降低漏電功耗，並已經成為業界流行的多閾值CMOS（MTCMOS）設計。然而，當開啟使用MTCMOS開關的電路時可能會出現一個大的湧入電流和動態電壓降 (IR drop)。這可能反過來導致電路的誤動作。在本論文，我們提出了一個新的系統架構，用來產生一個適當的電源開關的順序以控制電源門控領域 (power-gated domain) 的湧入電流，同時能大幅度地減少電源開啟的時間和減少活動域 (active domain) 的動態電壓降。我們還提出了一個可編程的骨牌式延遲電路來產生電源開關控制信號。根據一個先進的工業設計的實驗結果顯示，我們所提議的系統架構可以成功地限制湧入電流、大限度地減少開機時間並減少動態電壓降。結果進一步驗證了我們所提議的系統架構在處理超過八萬個電源開關和十億個電晶體以上之大型設計的效能。

Power gating is effective for reducing standby leakage power as multi-threshold CMOS (MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. In this thesis, we propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of active domains. We also propose a configurable domino-delay circuit for implementing the power-up sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.

Abstract    I
Contents    II
List of Tables    IV
List of Figures    V
Chapter 1 Introduction    1
Chapter 2 Background    5
2.1 On-chip Power Gating    6
2.2 Multi-domain MTCMOS Design    7
2.2.1 Power-Gated Architecture Using Header Switches    9
2.2.2 Power Switch Allocation    10
2.2.3 Power Switch Control Scheme    12
2.3 Previous Work on Inrush Current Control    14
2.3.1 Sizing and Slew Rate Control    14
2.3.2 Scheduling    15
2.3.3 Mother-daughter Switch Enabling    16
2.4 Dynamic IR Drop during Power-mode Transition    18
Chapter 3 Problem Formulation and Modeling    21
3.1 Problem Formulation    21
3.2 Modeling    22
3.2.1 Virtual Rail Voltage Modeling    22
3.2.2 Effective Modeling for Power Ramp-up Analysis    24
Chapter 4 Proposed Framework    30
4.1 Proposed Power-Up Sequencing Algorithm    30
4.2 Illustrated Example for Power-up Sequencing    32
4.3 Heuristic for Dynamic IR Drop Mitigation    35
4.4 Configurable Domino-delay Circuit    38
4.5 Power Switch Routing    39
4.6 Performance Analysis    42
4.7 Post-Silicon Tuning for Variation Control    43
Chapter 5 Experimental Results    46
Chapter 6 Conclusion and Future Work    60
References    62

                                

[1] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1 V high speed digital circuit technology with 0.5 um multi-threshold CMOS,” in Proc. IEEE 6th Int. Annu. ASIC Conf., 1993, pp. 186–189.
[2] M. Anis and M. Elmastry, “Multi-Threshold CMOS digital circuits, managing leakage power.” Kluwer Academic Publishers, 2003.
[3] C. Long and L. He, “Distributed sleep transistors network for power reduction,” in Proc. DAC, 2003, pp. 181–186.
[4] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proc. DAC, 2002, pp. 480–485.
[5] J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. DAC, 1997, pp. 409–414.
[6] J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns,” in Proc. DAC, 1998, pp. 495–500.
[7] C. Hwang, C. Kang, and M. Pedram, “Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs,” in Proc. ISQED, 2006, pp. 741–746.
[8] S. Kim, S. V. Kosonocky, and D. R. Knebel, “Understanding and minimizing ground bounce during mode transition of power gating structures,” in Proc. ISLPED, 2003, pp. 22–25.
[9] A. Davoodi and A. Srivastava, “Wake-up protocols for controlling current surges in MTCMOS-based technology,” in Proc. ASP-DAC, 2005, pp. 868–871.
[10] M. Keating, D. Flynn, R. Aitken, A. Gibsons, and K. Shi, Low Power Methodology Manual for System on Chip Design, New York: Springer, 2007, ch. 14, pp. 225–247 [Online]. Available: http://www.lpmm-book.org
[11] A. Ramalingam, A. Devgan, and D. Z. Pan, “Wake-up scheduling in MTCMOS circuits using successive relaxation to minimize ground bounce,” J. Low Power Electron, vol. 3, no. 1, pp. 28–35, Apr. 2007.
[12] Y. T. Chen, D. C. Juan, M. C. Lee, and S. C. Chang, “An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon,” in Proc. ICCAD, 2007, pp. 779–782.
[13] H. Jiang and M. Marek-Sadowska, “Power gating scheduling for power/ground noise reduction,” in Proc. DAC, 2008, pp. 980–985.
[14] Y. Lee, D. K. Jeong, and T. Kim, “Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits,” in Proc. ICCAD, 2008, pp. 169–172.
[15] A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino, “Design of a flexible reactivation cell for safe power-mode transition in power gated circuits,” IEEE Trans. Circuits Syst. I, vol. 56, no. 9, pp. 1979–1993, Sep. 2009.
[16] S. H. Chen, “Apparatus and Methods for Programmable Power-Up Sequence.”, U.S. and C.N. patent pending, Nov. 12, 2009.
[17] D. Juan,Y. Chen, M. Lee, and S. Chang, “An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp. 246–255, Feb. 2010.
[18] H. Jiao and V. Kursun, “Ground bouncing noise aware combinational MTCMOS circuits,” IEEE Trans. Circuits Syst. I, vol. 57, no. 8, pp. 2053–2065, Aug. 2010.
[19] S. H. Chen, Y. L. Lin, Mango C.-T. Chao, “Power-up Sequence Control for MTCMOS Designs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-11, November 2012.
[20] Y. M. Wang, S. H. Chen and Mango C.-T. Chao “An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs,” in Proc. ASP-DAC, 2012, pp. 59–65.
[21] Y. M. Chen and S. H. Chen, “Simultaneous Control of In-rush Current and Dynamic IR Drop in MTCMOS Designs Using Hamiltonian-cycle Routing.” Chip Design, Internet: http://chipdesignmag.com/display.php?articleId=5128, Mar. 27, 2012 [Apr. 20, 2012].
[22] S. H. Chen and J. Y. Lin, “Experiences of low power design implementation and verification,” in Proc. ASP-DAC, 2008, pp. 742–747.
[23] S. H. Chen, “ARM 1176 DVFS Chip Implementation and Verification with CPF,” in Cadence Design Systems, Inc. CDNLive Conference, Taiwan, 2009. (Best Presentation Award)
[24] S. H. Chen and J. Y. Lin, “Implementation and Verification Practices of DVFS and Power Gating,” in Proc. of VLSI Design, Automation and Test (VLSI-DAT), 2009, p.19–22.
[25] S. H. Chen, K. C. Chu, J. Y. Lin, and C. H. Tsai, “DFM/DFY practices during physical designs for timing, signal integrity, and power,” in Proc. ASP-DAC, 2007, pp. 232–237.
[26] T. M. Tseng, M. C.-T. Chao, C. P. Lu, and C. H. Lo, “Power-switch routing for coarse-grain MTCMOS technologies,” in Proc. ICCAD, 2009, pp. 39–46.
[27] S. H. Chen, “System and Method for Power Domain Isolation.” U.S. Patent 7 982 498, May 18, 2010.
[28] S. P. Mu, Y. M. Wang, H. Y. Yang, C.-T. Chao, and S. H. Chen, “Testing Methods for Detecting Stuck-open Power Switches in Coarse-Grain MTCMOS Designs,” in Proc. ICCAD, 2010, pp. 155–161.
[29] H. R. Pai and S. H. Chen, “Power control manager,” U.S. patent pending, May. 17, 2010.
[30] TSMC reference flow 8.0, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, 2007.
[31] RedHawk Users’ Manual, 10.1 ed. Apache Design Solutions Inc., San Jose, CA, 2010.
[32] Encounter digital implementation system user guide, Mar. Cadence Design System, Inc., San Jose, CA, 2011, pp. 491–532.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文