隨著製程不斷的演進，導線寬度以及導線和導線間的距離縮小，因此使得寄生電容值和電阻值都變大，由於這個原因造成一些影響:電阻電容延遲時間變長、電壓衰退、導線間的干擾，這些都會對晶片的效能造成影響。此外，導線間的距離降低也會增加介電值中金屬導線間的電場，因此時間相依介電質崩潰的研究和解決是必要的，在電路完全崩潰(硬式崩潰)之前發現有漏電流的增加，稱之為軟式崩潰，因為這個現象而推論在銅或超低k值的導線技術中，銅會向外游離到介電值中，因此而造成漏電流增加的現象，並且也讓金屬導線的電容值可能因此而改變，但是因為缺少即時的監測電容電路，我們無法得知在這段時間內金屬導線電容值的變化。
在本論文中研究一個即時電容測試電路，使用的是台積電65奈米的製程，採用20fF的電容值作為基準來設計監測電路，但因為主要的組成很簡單此電路很容易被用到其他更先進的製程。
利用米勒效應可以更進一步的增加對監測電容的敏感度，當電容兩端的訊號完全反向可以有效的放大電容值，在模擬中，當監測電容有5%變化時，可以觀察導的頻率變化是5.9%~6.7%。另一方面，除了量測頻率來監測電容值之外，也可以利用加上緩衝器的方式，量測緩衝器的電流或功率變化來得到電容值的變化。

Abstract
As the semiconductor technology advances, the interconnect line width and spacing shrink. The parasitic resistance and capacitance, as a result, increase. In turn, the increases in resistance and capacitance increases interconnect delay, IR drop and crosstalk. All these impact on chip performance. Furthermore, the reduction in line space increases the electric field in the dielectric between metal lines. Thus, time dependent dielectric breakdown (TDDB) needs to be investigated and resolved before the technology is fully qualified. Before the dielectric is completely breakdown (hard breakdown), leakage current has been observed to increase (soft breakdown). It has been theorized that in Cu/LK interconnect technology, Cu ion can be out-diffused into the dielectric, thus increases the leakage current. During this time, the interconnect capacitance might have been changed. Due to lack of a good real time monitor circuit, we do not know how does the interconnect capacitance change during this time.
A real-time capacitance monitor test circuit is developed in this thesis. It is implemented using TSMC 65LP technology. The target capacitance is 20fF. But, the circuit can be easily ported to other (more advanced) technology easily, since it consists of mostly simple inverters.
The sensitivity to the monitored capacitance is further increased by using Miller Effect. The signals on the two terminals of the capacitor is completely out of phase, thus magnifies the capacitance. Assuming a 5% change in monitored capacitance, 5.9% to 6.7% changes in frequency have been observed in simulations. On the other hand, instead of measure frequency, we also can measure current or power by connecting buffer chain to obtain the capacitance changing.

Reference
[1] C. Yao-Wen, C. Hsin-Wen, L. Tao-Cheng, K. Ya-Chin, T. Wenchi, J. Ku and L. Chih-Yuan, "Interconnect capacitance characterization using charge-injection-induced error-free (CIEF) charge-based capacitance measurement (CBCM)," IEEE Transactions on Semiconductor Manufacturing, Vol. 19, no. 1, pp. 50-56, 2006.
[2] C. Yao-Wen, C. Hsing-Wen, L. Tao-Cheng, K. Ya-Chin, T. Wenchi, K. Yen-Hui Joseph and L. Chih-Yuan, "Charge-based capacitance measurement for bias-dependent capacitance," IEEE Electron Device Letters, Vol. 27, no. 5, pp. 390-392, 2006.
[3] J. C. Chen, B. W. McGaughy, D. Sylvester and H. Chenming, "An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique," proceedings of International Electron Devices Meeting, 1996. IEDM '96. , pp. 69-72, 8-11 Dec. 1996, 1996.
[4] M. N. Chang, R. C. J. Wang, C. C. Chiu and K. Wu, "An efficient approach to quantify the impact of Cu residue on ELK TDDB," proceedings of 2009 IEEE International Reliability Physics Symposium, pp. 619-623, 26-30 April 2009, 2009.
[5] F. Chen, M. Shinosky, B. Li, J. Gambino, S. Mongeon, P. Pokrinchak, J. Aitken, D. Badami, M. Angyal, R. Achanta, G. Bonilla, G. Yang, P. Liu, K. Li, J. Sudijono, Y. Tan, T. J. Tang and C. Child, "Critical ultra low-k TDDB reliability issues for advanced CMOS technologies," proceedings of 2009 IEEE International Reliability Physics Symposium, pp. 464-475, 26-30 April 2009, 2009.
[6] C. Zhe, K. Prasad, L. Chaoyong, J. Ning and G. Dong, "Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects," IEEE Transactions on Device and Materials Reliability, Vol. 5, no. 1, pp. 133-141, 2005.