研究生: |
胡智閔 HU ZHI-MIN |
---|---|
論文名稱: |
700V LDMOSFET最佳化設計 The optimal design of 700V LDMOSFET |
指導教授: |
龔正
JENG JGONG |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 700V 、橫向雙擴散金氧半場效電晶體 、功率元件 、高壓元件 、超高壓元件 |
外文關鍵詞: | 700V, LDMOSFET, power device, high voltage device, ultra high voltage device |
相關次數: | 點閱:4 下載:0 |
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功率元件為了與平面製程整合,必須將傳統垂直式的元件結構改成橫向式的設計,因而可與低壓電路整合於同一晶片上。本論文探討的主軸結構為700伏特橫向雙擴散金氧半場效電晶體,其特性為在結構中的漂移區內填入P型場環(PTOP),使得導通電阻與元件面積獲得到比傳統橫向雙擴散金氧半場效電晶體更佳的元件性能。
本篇論文將P型場環與預漂移區摻雜(Pre-HVNW)結合於700伏特橫向雙擴散金氧半場效電晶體中作整合分析。改良500伏特結構過長的場氧化層,加入的P型場環讓元件整體的增加降低表面電場(RESURF)效果發揮更顯著;在固定元件尺寸之下的改良式結構比起傳統式結構可以擁有更優越的效能,而我們定義這種改良式結構為複合式橫向雙擴散金氧半場效電晶體。
最後透過電腦模擬的方式,可以清楚知道在不同條件設定下的崩潰電壓與導通電阻,有效的掌握其結構於最佳化的過程中,經過不斷地相互制衡後最終達到此次設計的目標700伏特,使得在同一尺寸下的元件能充分發揮空間利用率,並提出此複合式結構於未來開發的可能性。
In order to integrate power devices with planar IC process, the devices’ structure must be changed from the traditional vertical structure to lateral design, such that they can be integrated in the same chip. The main object of this thesis is to design a 700V LDMOSFET. The characteristic of the structure is to fill a PTOP in the drift region in order to decrease on-resistance and to produce better effect than traditional LDMOSFET.
In this thesis, we integrate the PTOP and Pre-HVNW into 700V LDMOSFET to further improve the performance of RESURF LDMOSFET. Devices’ performance is compared under the base of the same size.
Finally, we use computer simulation to obtain the detail of breakdown voltage and on-resistance under different situations. Careful tuning is made to obtain the optimum process conditions. The goal reached is that the device can sustain 700V breakdown voltage. The efficiency of the traditional device is indeed improved, and the results of the simulation also create the possibility of developing the complex structure in the future.
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[18]Pre-HVNW是TMSC之專利
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