低密度奇偶檢查(Low-density parity-check, LDPC) 碼為一具有強大改錯能力
的錯誤更正碼。近年來在多種通訊傳訊應用中, 當檢查節點(check node) 連結到變
量節點(variable node) 的個數較多時, 要實現一個高吞吐量且有效率的多模態低密
度奇偶檢查(LDPC) 解碼器仍然是個挑戰。在這篇論文中, 我們提出一種排程演算
法, 可將類循環低密度奇偶檢查(QC-LDPC) 碼的解碼運算切割成多個較小的運算
集合。排程演算法以欄位為基礎重新排序奇偶檢查矩陣(PCM) 的執行順序, 縮短
電路中最長路徑所需的抵達時間, 如此一來不但可以增加運算單元的使用率, 還可
以加快電路的操作頻率, 進而增加解碼吞吐量。基於此種以欄位為基礎的高吞吐量
多模態解碼器, 由於不同模態之間的切換存在著高複雜度的電路需要克服, 對此我
們利用類循環的特殊結構使得較複雜的繞線網絡可被簡單的多工器所取代, 在控制
電路方面也僅需要計數器加以控制即可。另外, 對於檢查節點運算值的儲存方式, 可
以使用記憶體以降低核心面積。使用這些技術, 我們可以完成一高吞吐量且支援多種
不同規範類循環低密度奇偶檢查碼解碼運算的多模態解碼器。綜合以上的方法, 我
們設計了一個適用於G.hn 規範的類循環低密度奇偶檢查碼解碼器電路。此電路晶
片在UMC 90奈米製程實現下, 核心面積為7.31 mm2, 且在操作頻率為400 MHz
時最高可到達到1.95Gb/s 的解碼吞吐量。

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