具無電容式假級輸出之雙低電位閘級驅動電路與可靠度分析研究

簡易檢索 / 詳目顯示

回結果列表

研究生：	袁愷廷 Yuan, Kai-Ting
論文名稱：	具無電容式假級輸出之雙低電位閘級驅動電路與可靠度分析研究 Study on Capacitorless Gate Driver On Array Circuit with Carrying Stage Output and Dual Low Voltages Levels
指導教授：	黃智方 Huang, Chih-Fang
口試委員:	劉柏村 Liu, Po-Tsun 盧志文 Lu, Chih-Wen 盧向成 Lu, Shiang-Cheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2022
畢業學年度：	111
語文別：	英文
論文頁數：	116
中文關鍵詞：	閘級驅動電路、無電容、假級、雙低電壓源
外文關鍵詞：	Gate Driver on Array, Capacitorless, Carrying stage, Dual low voltage sources
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

目前在市場上的產品所使用到的顯示技術有TFT-LCD、AMOLDE、Mini LED、Micro LED，其中以液晶薄膜顯示器(Thin-film-transistor liquid crystal display, TFT-LCD)具有龐大的市占率。由於面板產業所發展的成熟技術SOP(System-on-panel)、SOG(System-on-glass)，閘極驅動電路已取代Gate IC，藉此達到面板窄邊框。因為Gate IC會有過多的金屬繞線數而造成面積損耗，且在金屬線與顯示基板貼合的過程中造成的誤差也會導致面板良率的下降，因此透過使用薄膜電晶體製程將閘極驅動電路製作於玻璃基板上，可以減少製程成本和提高生產良率，尤其在中大尺寸的高解析度面板上，此技術更具有一定的優勢。
隨著科技的日新月異，移動式穿戴裝置的發展也日漸普及與蓬勃，如手機、智慧手錶、平板等等。人們對於TFT-LCD畫質的要求也逐漸提高，尤其是外觀和完美的視覺效果，因此窄邊框顯示器已逐漸成為面板產業的發展趨勢。本研究提出一種新穎的閘極驅動電路，透過特殊的抗雜訊區塊架構來達到無電容式和減少元件數量的設計，有利於窄邊框的應用，此外使用假級輸出和雙低電壓源來提升無電容技術所造成的信賴性問題，為了更進一步的了解電路在廣溫和長時間操作下的可靠度，提出了應用於閘極驅動電路的壽命預測方法，先預測關鍵元件在劣化後的電性圖，再透過電路模擬得到時間對最小供應電壓的作圖，最後通過量測電路的測試片來加以驗證此方法的精準度與正確性。

The display technology used in products on the market has TFT-LCD、AMOLDE、Mini LED, and Micro LED. Thin-film-transistor liquid crystal display (TFT-LCD) has the hugest market share among them. According to the ripe technology of the panel industry, like SOP(System-on-panel)、SOG(System-on-glass), the gate driver on array circuit has already replaced Gate IC to achieve panel narrow bezel. Gate IC will have too many metal windings and cause area loss, which will lead to a decrease in panel production yield when bonding the metal lines to the display substrate in the process. Hence, using the thin film transistor process can reduce the process cost and improve production yield to fabricate the gate drive circuit on the glass substrate. It has certain advantages in the medium and large size high-resolution panels especially.
With the flourishing of technology, the development of mobile devices is also more popular and vigorous, such as cellphones, smartwatches, flatbeds, etc. People about the demand for the image quality of TFT-LCD is gradually increasing, especially regarding appearance and perfect visual enjoyment. Therefore, a narrow bezel display has become a trend in the display industry. This research proposed a novel gate driver circuit through the special noise-free block to achieve the design of the no capacitor and reduce the number of devices, which is beneficial to the application of a narrow bezel. Furthermore, promoting the reliability issue of the capacitor-less technique, which uses the carrying stage and dual low voltage sources. To further know the reliability of the circuit under wide temperatures and long-term operation, proposing a lifetime prediction method for the gate driver circuit. First, predict the deteriorated electrical characteristics of key devices. And then get the time versus minimum supply voltage through circuit simulation. Finally, measuring the circuit test kit to verify the accuracy and correctness of this method.

摘要.................................................................................................i
Abstract............................................................................................ii
誌謝...............................................................................................iii
Contents............................................................................................iv
Figure Captions.....................................................................................vi
Table Captions.....................................................................................xii
Chapter 1  Introduction..............................................................................1
1 Overview of Liquid Crystal Displays (LCDs).......................................................1
1.1 Operation of TFT-LCDs......................................................................1
1.2 Driving System of Active Matrix LCD (AMLCD)................................................2
1.3 System on Panel (SOP)/System on Glass (SOG)................................................3
1.4 Amorphous Silicon TFTs for LCDs............................................................5
2 Motivation.......................................................................................6
3 Thesis Organization..............................................................................9
Chapter 2  Experimental Procedure...................................................................10
1 Experiment Flow.................................................................................10
2 Manufacture and Measurement Method of a-Si: H TFTs..............................................11
2.1 Process of a-Si: H TFTs...................................................................11
2.2 Parameter Extraction Methods..............................................................14
2.3 Layout Optimization.......................................................................15
Chapter 3  Electrical Characteristics and Device Model of a-Si: H TFTs..............................17
1 Transfer and Output Characteristics of a-Si: H TFTs.............................................17
2 Electrical Characteristics at Wide Temperature..................................................20
2.1 Electrical Characteristics at High Temperature............................................21
2.2 Electrical Characteristics at Low Temperature.............................................26
3 Models of a-Si TFTs in SmartSpice...............................................................27
Chapter 4  The Lifetime Prediction Method for GOA circuits through SmartSpice Simulation............28
1 Prior Arts Discussion and Design Consideration..................................................28
1.1 GOA circuit with low-level (Prior Art III)....................................................28
2 The Experimental Procedure of the Lifetime Prediction Method for GOA Circuits...................32
2.1 Measurement Results and Methods of Minimum Supply Voltage of 8T1C, 10T1C, 14T1C, and
16T1C.....................................................................................35
2.2 Analyze and Determine the Main a-Si TFTs that Affect the GOA Circuit Lifetime.............38
2.3 Measurement Results and Methods of the B[n] and C[n] Node Voltage.........................40
2.4 The Experimental Procedure of the IDS-VGS Predictions Stress Curve........................44
2.5 Prediction Results and Discussion.........................................................67
3 Summary.........................................................................................71
Chapter 5  Capacitorless GOA circuit with High Reliability for Narrow Bezel Display.................72
1 Prior Arts Discussion and Design Consideration..................................................73
1.1 Basic Function Blocks of GOA circuit (Prior Art Ⅰ).......................................73
1.2 GOA circuit with the noise-free block (Prior Art II)......................................75
1.3 GOA circuit for narrow bezel display (Prior Art IV).......................................76
2 Capacitorless GOA circuit with High Reliability for Narrow Bezel Display........................78
2.1 Circuit Schematic and Operation...........................................................85
2.2 Simulation Results and Analysis...........................................................89
2.2.1 Discussion of ST[N] Driving Noise-Free Block for the Proposed Circuit.............99
2.2.2 Discussion of Leakage Current of the A[N] node for the Proposed Circuit..........101
2.2.3 Discussion of Noise Sensitivity of the G[N] node for the Proposed circuit........103
2.3 Measurement Results and Discussion.......................................................104
3 Summary........................................................................................110
Chapter 6  Conclusions.............................................................................111
2 Future Work....................................................................................112
Reference..........................................................................................113
Vita...............................................................................................116


                                

[1] B. Chandar Shekar, J. Lee, and S. W. Rhee, "Organic thin film transistors: Materials, processes, and devices," Korean Journal of Chemical Engineering, vol. 21, no. 1, pp. 267-285, 2004.
[2] D. J. Cristaldi, S. Pennisi, and F. Pulvirenti, Liquid crystal display drivers: Techniques and circuits. Springer, 2009.
[3] J. Lee, "Gate driving circuit and gate driving method," ed: Google Patents, 2015.
[4] S. M. Sze, Y. Li, and K. K. Ng, Physics of semiconductor devices. John wiley & sons, 2021.
[5] Y. H. Tai, "Design and operation of TFT-LCD panels," Wu-Nan Culture Enterprise, vol. 3, pp. 97-100, 2006.
[6] T. C. Lu, H. W. Zan, and M. D. Ker, "Temperature coefficient of poly-silicon TFT and its application on voltage reference circuit with temperature compensation in LTPS process," IEEE transactions on electron devices, vol. 55, no. 10, pp. 2583-2589, 2008.
[7] W. J. Nam, J. H. Lee, H. J. Lee, H. S. Shin, and M. K. Han, "Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors," Journal of the Society for Information Display, vol. 14, no. 4, pp. 403-409, 2006.
[8] Y. H. Tai, C. C. Pai, B. T. Chen, and H. C. Cheng, "A source-follower type analog buffer using poly-Si TFTs with large design windows," IEEE electron device letters, vol. 26, no. 11, pp. 811-813, 2005.
[9] Y. C. Tarn, P. C. Ku, H. H. Hsieh, and L. H. Lu, "An amorphous-silicon operational amplifier and its application to a 4-bit digital-to-analog converter," IEEE journal of solid-state circuits, vol. 45, no. 5, pp. 1028-1035, 2010.
[10] D. R. Allee, L. T. Clark, R. Shringarpure, S. M. Venugopal, Z. P. Li, and E. J. Bawolek, "Degradation effects in a-Si: H thin film transistors and their impact on circuit performance," in 2008 IEEE International Reliability Physics Symposium, 2008: IEEE, pp. 158-167.
[11] Allee, D. R., Clark, L. T., Vogt, B. D., Shringarpure, R., Venugopal, S. M., Uppili, S. G., ... & O'Rourke, S. M., "Circuit-level impact of a-Si: H thin-film-transistor degradation effects," IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1166-1176, 2009.
[12] M. J. Powell, "The physics of amorphous-silicon thin-film transistors," IEEE transactions on Electron Devices, vol. 36, no. 12, pp. 2753-2763, 1989.
[13] R. I. Huq and S. Weisbrod, "Phase clocked shift register with cross connecting between stages," ed: Google Patents, 1995.
[14] Oh, J. H., Hur, J. H., Son, Y. D., Kim, K. M., Kim, S. H., Kim, E. H., ... & Jang, J., "15.2: 2.0 inch a‐Si: H TFT‐LCD with Low Noise Integrated Gate Driver," in SID Symposium Digest of Technical Papers, 2005, vol. 36, no. 1: Wiley Online Library, pp. 942-945.
[15] S. Edo, M. Wakagi, and S. Komura, "46.3: A 2.2 ″QVGA a‐Si TFT LCD with High Reliability Integrated Gate Driver," in SID Symposium Digest of Technical Papers, 2006, vol. 37, no. 1: Wiley Online Library, pp. 1551-1554.
[16] Jang, Y. H., Yoon, S. Y., Kim, B., Chun, M. D., Cho, H. N., Cho, N. W., ... & Chung, I. J., "Integrated gate driver circuit using a-Si TFT with dual pull-down structure," IDW Digest, p333, 2004.
[17] Yoon, S. Y., Jang, Y. H., Kim, B., Chun, M. D., Cho, H. N., Cho, N. W., ... & Chung, I. J., "P‐172L: Late‐News Poster: Highly Stable Integrated Gate Driver Circuit using a‐Si TFT with Dual Pull‐down Structure," in SID Symposium Digest of Technical Papers, 2005, vol. 36, no. 1: Wiley Online Library, pp. 348-351.
[18] F. Libsch and J. Kanicki, "Bias‐stress‐induced stretched‐exponential time dependence of charge injection and trapping in amorphous thin‐film transistors," Applied Physics Letters, vol. 62, no. 11, pp. 1286-1288, 1993.
[19] K. H. L. C. C. Tseng, S. C. Liu, C. C. Chang, L. Y. Chien, "Gate driver for liquid crystal display," TW Patent Appl. No. I575498, 2017.
[20] K. J. C. J. H. Chen, C. E. Chen, P. F. Chung, X. Y. Lu, "Circuit for gate drivers on arrays with common noise free function," TW Patent Appl. No. I727820, 2021.
[21] P. T. Liu, G. T. Zheng, and Y. C. Lin, "Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application," Journal of the Society for Information Display, vol. 27, no. 1, pp. 21-33, 2019.
[22] Z. Wang, H. Huang, C. Dai, and D. Xia, "P‐12: Novel 1‐to‐N Architecture of Bidirectional Gate Driver for Ultra‐Narrow‐Border Display," in SID Symposium Digest of Technical Papers, 2018, vol. 49, no. 1: Wiley Online Library, pp. 1223-1226.
[23] K. Myny, J. Genoe, and W. Dehaene, "Organic and metal-oxide thin-film transistors," Robust Design of Digital Circuits on Foil, pp. 9-32, 2016.
[24] B. Jiang and T. Xia, "Model analysis of multi-finger MOSFET layout in ring oscillator design," in 2011 12th International Symposium on Quality Electronic Design, 2011: IEEE, pp. 1-6.
[25] Z. Hu, C. Liao, W. Li, L. Zeng, C. Y. Lee, and S. Zhang, "Integrated a-Si: H gate driver with low-level holding TFTs biased under bipolar pulses," IEEE Transactions on Electron Devices, vol. 62, no. 12, pp. 4044-4050, 2015.
[26] C. C. Shih, Y. S. Lee, K. L. Fang, C. H. Chen, and F. Y. Gan, "A current estimation method for bias-temperature stress of a-Si TFT device," IEEE Transactions on Device and Materials Reliability, vol. 7, no. 2, pp. 347-350, 2007.
[27] Y. S. L. C. W. Tung, W. L. Lin, "Display device and gate driver on array," TW Patent Appl. No. I567710, 2017.
[28] K. J. C. J. H. Chen, C. E. Chen, P. F. Chung, X. Y Lu, "Circuit for gate drivers on arrays with stage-crossing noise free function," TW Patent Appl. No. M604476, 2020.
[29] K. J. C. J. H. Chen, C. E. Chen, P. F. Chung, X. Y Lu, "Circuit for gate drivers on arrays with common noise free function," TW Patent Appl. No. I727820, 2020.

簡易檢索 / 詳目顯示

相關論文