超大型積體電路製程已進入了深次微米的時代，使得更複雜的電路設計得以被製造。另一方面，在目前的設計自動化流程中，必需為這些複雜的電路考慮許多不同的需求，例如低功率(Low power)，晶片面積最小化(Area minimization) ，較高的效能(High timing performance)，可測試性(testability)以及減少晶片中的過熱區域(Reduce hot - spot)…等等。
在目前的設計自動化流程中，配置(Placement)的步驟扮演了重要的角色。許多考量，例如電路的效能，面積大小，可繞線度等等，都可以藉由將電路裡的單元(Cell)配置最佳化來達成。特目別是對於電路的效能而言，配置方法的好壞具有相當重大的影響。隨著半導體製程的進步，單元的延遲(Cell delay)被縮短的程度遠大於電路內部連線的延遲(Interconnect delay)，因此電路內部連線的長度對於電路效能的影響變得更加顯著；而配置的步驟決定了電路內部連線的最短長度。若想達成高效能的目標，就必需減少電路內部連線的長度。
所謂的效能導向漸進式配置方法(Timing - driven incremental placement)指的是在已有初始配置(Initial placement)的情形下，將現有的配置稍做更動，以達到符合時序限制(Timing constraint)的要求。時序(Timing)很重要，但並不是唯一的考量。有時候我們會以低功率，晶片面積的最小化等等為目標去決定如何配置，但配置結果卻違反了時序的限制. 在這種情形下，我們需要一種效能導向漸進式配置的演算法，在盡量減少初始配置被破壞的前提下去改善電路的效能。在本篇論文中，我們把[1] 的方法加以改良，提出一種新的效能導向漸進式配置演算法，實驗結果證明我們的方法不但能改進電路效能，並且能將初始配置的破壞減少到最低。

Timing-driven incremental placement is required when an initial placement violates the
timing constraint. It often occurs when the objective of an initial placement is power or
area. If the initial placement does not satisfy the timing constraint, we need timing-driven
incremental placement algorithm to improve timing while minimize the disturbance to the
initial placement. In our thesis, we will study timing-driven incremental placement problem.

[1] Wonjoon Choi and Kia Bazargan, \Incremental Placement for Timing Optimization",
Proceedings of ICCAD, 2003.
[2] Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin,
Yegna Parasuram, and Bill Halpin, \How Accurately Can We Model Timing In A
Placement Engine?", Proceedings of DAC , 2005.
[3] Cristinel Ababei, Selvakkumaran Navaratnasothie, Kia Bazargan, George Karypis,
\Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization",
Proceedings of ICCAD , 2002.
[4] Bill Halpin, C.Y. Roger Chen, Naresg Sehgal, \Timing Driven Placement using Physical
Net Constraints", Proceedings of DAC, 2001.
[5] Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill
Halpin, \Timing Driven Force Directed Placement Physical Net Constraints", Proceed-
ings of ISPD , 2003.
[6] Zhong Xiu, Rob A. Rutenbar, \Timing-Driven Placement by Grid-Warping", Proceed-
ings of DAC, 2005.
[7] Min Pan, Natarajan Viswanathan and Chris Chu, \An E±cient and E®ective Detailed
Placement Algorithm", Proceedings of ICCAD, 2005.
[8] Yutaka Tamiya, \Performance Optimization Using Separator Sets", Proceedings of IC-
CAD , 1999.
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[9] Yih-Chih Chou and Youn-Long Lin, \E®ective Enforcement of Path-Delay Constraints
in Performance-Driven Placement", IEEE Transactions on Computer-Aided Design of
Intergrated Circuits and Systems, VOL.21, No.1, January 2002.
[10] http://vlsicad.eecs.umich.edu/BK/PlaceUtils/
[11] http://www.synopsys.com