為了提高記憶體的可靠度或良率，容錯(fault tolerance)技術時常被用來修復記憶體上發生的永久性或暫時性錯誤。在記憶體的儲存與讀寫動作中，錯誤更正碼(error correction code)藉由儲存在記憶體內額外的檢查碼和編解碼技術，即時地更正與偵查讀取資料內的錯誤；可提昇記憶體使用期間的可靠度與出廠時的良率。另一方面，在虛擬靜態記憶體(PSRAM）內常常藉由延長再新(refresh)週期來達到減低功耗的目的，但是，此舉將使得體質不良的記憶體單元發生資料錯誤。本論文中，我們提出一種新型的錯誤更正碼架構，以長編碼(long codewords)減少檢查碼的成本，來修復並保護延長再新（refresh）週期的虛擬靜態記憶體內的資料，並同時解決錯誤掩蓋(error masking)的問題。針對新型架構中的檢查碼核對矩陣(parity check matrix)，我們也提出系統化的產生方法。實驗結果顯示，針對擁有16位元輸出入的256MB PSRAM，我們使用的(72,64)長編碼僅僅增加了0.2%的電路面積與3.5奈米秒的時間延遲，卻比傳統(22,16)編碼方法減少了3倍的檢查碼使用量，也有效的消除了錯誤掩蓋的問題。
另一方面，三維整合積體電路(3D IC)中，穿矽孔(TSV)提供了大量且低負載的連線方式，可以降低功耗並提升速度與信號頻寬。如何有效的提升三維整合積體電路的良率是當務之急。在晶圓磨薄前(pre-thin)的穿矽孔結構類似於動態記憶體(DRAM)的記憶單元，本論文中，我們提出三種在晶圓磨薄與堆疊前的穿矽孔測試技術。針對盲洞(blind)穿矽孔製程，借鏡動態記憶體內的感測放大(sense amplification)技術，我們提出了充放電法(charge-discharge test)與電荷分配法(charge-sharing test)；針對透孔(open-sleeve)穿矽孔，我們提出了分電壓法(voltage- dividing)法。我們提出的測試技術可以在晶圓測試階段(wafer-level testing)，檢查出晶片上的瑕疵穿矽孔並丟棄該晶片，以節省堆疊不良晶片所導致的後續製造與測試的成本損失。藉由穿矽孔電氣模型，實驗模擬結果顯示，針對直徑5um、深度50um、60fF的盲洞穿矽孔，電容值變動範圍在正負10%以上的有瑕疵穿矽孔可以被充放電法有效的篩選出來。而製程變動(process variation)的蒙地卡羅實驗顯示，針對4010fF的盲洞穿矽孔，在電荷分配法中，一個測試模組可以被100個穿矽孔共用，且誤判率(overkill rate)小於6%。針對170毫歐姆的透孔穿矽孔，分電壓法可以有效測試出高阻值的斷裂等瑕疵。

Error control codes or error correction codes (ECC) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, in this thesis, we present a parallel encoding and decoding ECC scheme to reduce refresh power for an industrial pseudo SRAM (PSRAM) with long codewords. We also propose a systematic way to generate the parity check matrix and the parity correction mechanism to reduce the operating power for the proposed scheme. As for the 70ns access time of the 256MB PSRAM with the (72,64) code and 16-bit I/O, experimental results show that the new ECC scheme can be integrated with the READ/WRITE operations with about 0.2% circuit area overhead and less than 3.5ns encoding/decoding time. The parity overhead of the new ECC scheme is 12.5% instead of 37.5% as in the conventional scheme with the (22, 16) code The proposed architecture provides a flexible solution for memories with different widths of ECC codewords and I/O ports, without the error masking effect or reduction in reliability.
To provide a small form factor, reduce power consumption, increase performance and memory density, three dimensional integration circuits (3D IC) seem an inevitable solution for these requirements. For the challenges of 3D IC, yield improvement is the most critical and emergency issue. Most works in 3D IC testing focus on the post-bond interconnection test. However, pre-bond test is preferred for the 3D IC, since it reduces stacking yield loss and thus saves the following cost. In this thesis, we introduce three pre-bond TSV low-frequency test schemes for blind-hole TSVs and open-sleeve TSVs by performing on-chip screening before wafer thinning and bonding. The first two schemes are for blind-hole TSVs, which have one end floating, using the charge-discharge and charge-sharing techniques, respectively, while the later is commonly seen in DRAM. The third scheme is for open-sleeve TSVs, which have one end shorted to the substrate, using a voltage-dividing technique commonly seen in ROM. By virtue of the inherent capacitive and resistive characteristics, we detect the TSVs out of a specified range as anomalies, taking into account the effects of process variations in the detection circuitry. The statistical design by Monte Carlo simulation using TSMC 65nm low-power process shows that for blind-hole TSVs, the best overkill ratio can be below 6%, but for open-sleeve TSVs, the inherent limitations restrict the applicability and the results vary. Our implementation enjoys little area overhead, requiring only a simple sense amplifier and a write buffer that are shared among a number of TSVs. Reducing the number of TSVs that share a test module will reduce the test time, but increase the area overhead. For blind-hole TSVs, the parallelism also affects the overkill and escape rates.

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