具備穩壓功能振盪器之鎖相迴路設計｜國立清華大學博碩士論文庫

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研究生：	黃楷翔 Kai-Hsiang Huang
論文名稱：	具備穩壓功能振盪器之鎖相迴路設計 A Supply-Noise-Insensitive PLL Design with A Supply Regulated VCO
指導教授：	黃柏鈞 Po-Chiun Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	96
語文別：	中文
論文頁數：	64
中文關鍵詞：	鎖相迴路、壓控振盪器、抖動、相位雜訊、電源雜訊、穩壓器
外文關鍵詞：	PLL, VCO, jitter, phase noise, supply noise, regulator
相關次數：	點閱：2 下載：0
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鎖相迴路器已經被廣泛的應用在數位系統內以產生精準的時脈。時脈抖動是鎖相迴路設計重要的議題之ㄧ，因為時脈的抖動會限制數位系統所能操作的最高頻率。隨著製程的進步，電路的工作電壓逐漸下降，和鎖相迴路器整合在一起的數位電路也越來越多，如此會造成鎖相迴路器的電源線上來自數位電路的切換雜訊越來越大，使得鎖相迴路器的抖動效能容易被這些電源線上的雜訊所主宰。因此一個能抵抗電源雜訊的鎖相迴路設計是必要的。

除了電源雜訊的問題之外，壓控振盪器的頻率調整範圍、鎖相迴路的頻寬以及輸出時脈的抖動效能等常常是鎖相迴路設計的規格。這篇論文對鎖相迴路提出一個設計方法，使得鎖相迴路除了有能夠抵抗電源雜訊的優點之外，也能夠同時滿足這些規格。這個設計方法因為具有一般性，所以也適用在不同的規格上。

根據這個設計方法，一個鎖相迴路器以0.18微米的互補式金氧半導體製程製造，晶片面積約為。當晶片的工作電壓在1.8伏時，量測到的鎖相迴路輸出頻率約為0.24GHz到2.4GHz。在頻率為2.4GHz時，整個晶片功率消耗約為18mW。當沒有外加雜訊在壓控振盪器的電源上時，輸出時脈的方均根抖動值約為時脈週期的1.3%。當外加一方波雜訊在壓控振盪器的電源線上時，2.4GHz的輸出時脈對電源雜訊的敏感度為1%的電源電壓變化會造成0.3%的時脈週期變化。

Phase locked-loops (PLLs) are widely used in digital systems to generate well-timed clocks.
Clock timing jitter is one of the most significant issues since any timing uncertainty limits the
speed of digital systems. Scaling trends will shrink supply voltage and induce more switching
noise from digital circuits to the power supply. The supply noise perturb the more sensitive
blocks, especially for VCO in a PLL, and degrade PLL jitter performance. Therefore, it is
desirable to design a VCO with good supply noise immunity.
VCO tuning range and PLL output jitter are two common specifications for PLL design. This
thesis proposes a design methodology for a supply-noise-insensitive PLL to meet VCO tuning
range and PLL jitter requirements. The proposed methodology is general thus it is flexible for
different applications.
Based on the proposed design flow, a phase-locked loop (PLL) has been fabricated in 0.18-um /
1.8V CMOS technology. Chip area of the core circuit is 0:18mm2. Measurement results show
that the PLL can generate clock signals ranging from 0.24GHz to 2.4GHz. Power consumption
is about 18mW at 2.4GHz. Under quiet supply, PLL output long-term RMS jitter is about 1.3%
UI over the tuning range. When a square wave noise is injected to VCO supply, PLL output
clock has sensitivity 0.3%-clock period / 1%-VDD at 2.4GHz.

Contents
Introduction 1
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Phase-Locked Loop Fundamentals 3
1 PLL Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PLL Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Phase-Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . 5
2.2 Voltage-Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . 6
2.3 Charge-Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . 6
2.4 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Loop Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Noise in PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 PLL Output Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Supply and Substrate Noise . . . . . . . . . . . . . . . . . . . . . . 11

Supply Regulated VCO Design Background 13
1 Oscillator Period Jitter Due to Thermal Noise . . . . . . . . . . . . . . . . . 13
2 Oscillator Period Jitter Due to Supply Noise . . . . . . . . . . . . . . . . . . 17
3 Typical Structure of Supply Regulated VCO . . . . . . . . . . . . . . . . . . 19
3.1 Loop Analysis of Supply Regulated VCO . . . . . . . . . . . . . . . 20
4 Comparison of Different Delay Cells . . . . . . . . . . . . . . . . . . . . . . 25
Design and Analysis of PLL with Supply Regulated VCO 27
1 PLL Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1 Phase Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . . 27
1.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5 Supply Regulated VCO . . . . . . . . . . . . . . . . . . . . . . . . . 31
2 Design Flow for Supply Regulated VCO . . . . . . . . . . . . . . . . . . . . 31
Measurement Result 52
1 Measurement under Quiet Supply . . . . . . . . . . . . . . . . . . . . . . . 53
2 Measurement under Noisy Supply . . . . . . . . . . . . . . . . . . . . . . . 56
Conclusion and FutureWork 63
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

List of Figures
1 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Individual blocks in a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Operation of a PFD: (a) fref=fck and (b) fref >fck . . . . . . . . . . . . . . 5
4 A three-stage ring VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Linear model of a charge-pump PLL . . . . . . . . . . . . . . . . . . . . . . 8
6 Third-order PLL open-loop transfer function . . . . . . . . . . . . . . . . . . 8
7 Noise sources in a PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1 Illustration of oscillator period jitter . . . . . . . . . . . . . . . . . . . . . . 14
2 Illustration of oscillator phase noise . . . . . . . . . . . . . . . . . . . . . . 14
3 Schematic of VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Width of delay cell on phase noise . . . . . . . . . . . . . . . . . . . . . . . 17
5 Kvco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Oscillator period jitter due to supply noise . . . . . . . . . . . . . . . . . . . 18
7 Typical supply regulated VCO . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Model VCO as a resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

LIST OF FIGURES
9 I-V curve of VCO and diode-connected MOS . . . . . . . . . . . . . . . . . 21
10 Small-signal model for PSRR analysis . . . . . . . . . . . . . . . . . . . . . 21
11 Typical open and closed loop frequency response . . . . . . . . . . . . . . . 24
12 Phase margin, !a , as a function of x . . . . . . . . . . . . . . . . . . . . . . 24
13 Common delay cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1 Supply-regulated PLL block diagram . . . . . . . . . . . . . . . . . . . . . . 28
2 Schematic of PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Schematic of charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Schematic of loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Schematic of divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Schematic of supply regulated VCO . . . . . . . . . . . . . . . . . . . . . . 32
7 VCO tuning curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 PLL output phase noise from charge pump . . . . . . . . . . . . . . . . . . . 35
9 PLL output phase noise from loop filter . . . . . . . . . . . . . . . . . . . . 36
10 PLL loop bandwidth and phase margin . . . . . . . . . . . . . . . . . . . . . 36
11 Reference clock phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12 Jitter accumulation in PLL oscillator . . . . . . . . . . . . . . . . . . . . . . 38
13 Wvco on phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
14 Power and current consumption of VCO . . . . . . . . . . . . . . . . . . . . 40
15 VCO phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16 PLL output long-term RMS jitter (due to VCO noise) over the tuning range . 41

LIST OF FIGURES
17 Predicted PLL output phase noise . . . . . . . . . . . . . . . . . . . . . . . 42
18 Decoupling capacitor on supply noise rejection . . . . . . . . . . . . . . . . 43
19 SR VCO loop gain as fo=2.6GHz . . . . . . . . . . . . . . . . . . . . . . . . 44
20 SR VCO loop gain as fo=0.6GHz . . . . . . . . . . . . . . . . . . . . . . . . 44
21 (a) Regulator bandwidth and (b) PLL loop phase margin over the tuning range 45
22 Supply regulated VCO power consumption . . . . . . . . . . . . . . . . . . 46
23 Length of OP input stage on VCO phase noise . . . . . . . . . . . . . . . . . 46
24 Length of bias circuit on VCO phase noise . . . . . . . . . . . . . . . . . . . 47
25 SR VCO with device size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
26 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
27 Svdd over the tuning range . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
28 Step response of VCO output . . . . . . . . . . . . . . . . . . . . . . . . . 50
29 Schematic of level shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
30 VCO output waveform after level shifter . . . . . . . . . . . . . . . . . . . . 50
31 Summary of supply regulated VCO design flow . . . . . . . . . . . . . . . . 51
1 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3 Measured clock at divider output: (a) 15MHz and (b) 150MHz . . . . . . . . 54
4 Measured clock at divider input: (a) 0.24GHz and (b) 2.4GHz . . . . . . . . 54
5 Measured VCO tuning curve . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Measured VCO and PLL power consumption over the tuning range . . . . . . 55

LIST OF FIGURES
7 PLL output long-term RMS jitter: (a) fvco=0.24GHz and (b) fvco=2.4GHz . 56
8 Phase noise at divider output . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9 Measured PLL output long-term RMS jitter over the tuning range . . . . . . 57
10 Measurement setup for clock sensitivity due to supply noise . . . . . . . . . 58
11 Measured jitter histogram as supply noise amplitude = 50mV . . . . . . . . . 59
12 Measured jitter histogram as supply noise amplitude = 230mV . . . . . . . . 59
13 PLL output clock sensitivity over the tuning range . . . . . . . . . . . . . . . 60
14 PLL output jitter response to supply noise . . . . . . . . . . . . . . . . . . . 61
15 Performance comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
16 VCO control signal under different supply noise tests . . . . . . . . . . . . . 62

List of Tables
1 Period jitter for different MOS width . . . . . . . . . . . . . . . . . . . . . 16
2 Ring oscillator measured data in [9] . . . . . . . . . . . . . . . . . . . . . . 26
1 Design target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2 PLL loop parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1 Performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

                                

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