電源閘控(power gating)是一種有效減少漏電流的方法。設計電源閘控電路必須限制電路在喚醒程序(wakeup process)中產生的浪湧電流(surge current)大小。通常來說，喚醒排程技術(wakeup scheduling)被用來控制每個睡眠電晶體打開的時間。這篇論文中，我們利用電壓感測器比較預先設計的參考電壓(reference voltage)，以及虛擬接地(virtual ground)的電壓值，再利用比較的結果決定睡眠電晶體打開的時間。我們討論使用電壓感測器的特性以及最佳化的方法。另外，因為最短喚醒時間的喚醒排程技術需要消耗大量硬體資源，我們提出新的喚醒排程技術表示法，考慮喚醒時間及硬體資源的損益平衡。實驗結果顯示，增加一些喚醒時間，能大量減少硬體資源的消耗。

Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. Normally, a wakeup scheduling is required to control turn-on times of sleep transistors. In this thesis, we adopt a voltage sensor to compare pre-designed reference voltages with the virtual ground voltage and use the comparison result to determine turn-on times of sleep transistors. Special properties and optimizations of using voltage sensors are discussed. Since a wakeup scheduling with fast wakeup time may require significant hardware resources, we propose a new wakeup scheduling formulation which considers the trade-off between wakeup times and hardware resources. Our experimental results show that with small increases on wakeup times, we can reduce significant hardware resources for a power gating design.

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