研究生: |
李偉銍 Lee, Wei-Zhi |
---|---|
論文名稱: |
應用矽鍺氧化穿隧層對奈米線電荷捕捉式快閃記憶體元件操作特性影響研究 Application of SiGeO tunneling layer on Operation Characteristics of Nanowire Charge-Trapping Flash Memory Devices |
指導教授: |
張廖貴術
Chang-Liao, Kuei-Shu |
口試委員: |
趙天生
Chao, Tien-Sheng 劉致為 Liu, Chee-Wee |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 英文 |
論文頁數: | 93 |
中文關鍵詞: | 矽鍺氧化穿隧層 |
外文關鍵詞: | SiGeO tunneling layer |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
由於平面式元件微縮面臨挑戰,3D快閃記憶體技術變得越來越重要。記憶體元件除了追求高儲存密度之外,同時保有良好的電性特性以及可靠度的元件是被期待的。由於近年來矽化鍺和鍺掩埋式通道被應用於快閃記憶體之操作特性提升,本論文首先以鍺沉積層提供較多的載子注入、降低氧化層能障等性質改善元件操作特性。同時,將矽化鍺和鍺沉積層摻雜了磷和硼,以觀察不同通道介面的內建電場來分析其對元件操作特性的影響,最後探討利用電荷反轉式元件改善無接面式元件抹除速度上的缺點。
第一部分,將矽化鍺及鍺沉積層掩埋通道應用在多晶矽無接面快閃記憶體元件上。而從實驗結果得知,矽化鍺和鍺的掩埋通道元件在寫入速度和抹除速度上相較於無掩埋式通道都有較好的表現。這可歸功於鍺材料的特性,較窄的能隙可以提供較多載子、穿隧層電場較強,穿隧層能障也較低,電子跨越能障相對容易。再者,矽鍺及鍺掩埋通道元件的耐久力也相較好,可能因為較快的寫抹速度,也就是較短寫入時間下減少了氧化層的損傷。
第二部份,針對矽化鍺及鍺掩埋通道摻雜磷和硼,讓沉積層與通道產生PN接面和內建電場。原本預計觀察對沉積層進行摻雜後接面處所產生內建電場的效應,但後來發現鍺穿隧層的厚度才是占有較主要的影響原因。從實驗結果來看,鍺穿隧層較厚的元件有著較快的寫抹速度、良好的元件耐久力。內建電場機制之影響不大,能障較低才是影響操作特性的主要原因。
第三部分,探討掩埋式通道中摻雜磷和硼反轉式通道元件,由前一部分得知氧化鍺穿隧層越厚寫抹速度越快,但無接面式快閃記憶之元件之抹除速度較緩慢,因此採用反轉式元件。而根據實驗結果,電荷反轉式元件在抹除速度和元件耐久力也有所提升。
3D flash technology is becoming more important, because the scaling down planar device faces challenge. In addition to high storage density, flash device with good electrical characteristic and reliability are required. In recent years, buried channel such as SiGe and Ge deposition layer applications are applied used to improve operation characteristics of flash device. Therefore, in this thesis, operation characteristics of device are improved by Ge buried channel, which can provide more injection carriers and lower energy barrier height. Operation characteristic of devices with different build-in electric field near channel and tunneling oxide interface formed by P/B doping junction are analyzed and discussed. Finally, erase speeds of flash device are enhanced by inversion mode device are compared to junctionless.
In the first part, SiGe and Ge deposition buried channels are applied to poly silicon junctionless flash memory device. From experiment result, program and erase speeds of devices with SiGe and Ge buried channels are faster than those without buried channel device. This improvement can be attributed to Ge with more injection carriers by a narrower bandgap, high electric field in tunneling layer, and lower energy barrier. In addition, endurance performance of SiGe, Ge buried channel device are good because of fast program speed, namely shorter program time which reduces the damage in tunneling oxide layer.
In the second part, SiGe/Ge buried channels are doped with phosphorus and boron to forms PN junction and create a built-in electric field. Although in effects of built-in electric field of PN junction formed with different doping are expected, the thickness of GeO2 in the dominant faster than our observation. From experiment at result, device with a thicker GeO2 shows faster program/erase speed and good endurance performance. Effects of the built-in electric field are minor, because operation characteristic are influence by the tunneling path.
In the third part, IM flash memory device with Ge buried channel and P/B doping is studied, the program/erase speeds of devices with more GeO2 are faster and junctionless flash memory device has slower erase speed. From experiment at result, the IM device shows faster erase speed and good endurance performance.
[1] San, K.T.; Kaya, C.; Ma, T.P., "Effects of erase source bias on Flash EPROM device reliability," Electron Devices, IEEE Transactions on, vol.42, no.1, pp.150-159, Jan 1995.
[2] White, M.H.; Adams, D.A.; Jiankang Bu, "On the go with SONOS," Circuits and Devices Magazine, IEEE, vol.16, no.4, pp.22-31, Jul 2000.
[3] White, M.H.; Yang Yang; Ansha Purwar; et al., "A low voltage SONOS nonvolatile semiconductor memory technology," Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, pp.52-57, 24-26 Jun 1996.
[4] Jiankang Bu; White, M.H., "Retention reliability enhanced SONOS NVSM with scaled programming voltage," Aerospace Conference Proceedings, 2002. IEEE, vol.5, pp.5-2383,5-2390, 2002.
[5] Kahng, D.; Sze, S.M., "A floating gate and its application to memory devices," Bell System Technical Journal, The, vol.46, no.6, pp.1288-1295, July-Aug. 1967
[6] Simon M. Sze, Kwok K. Ng, Physics of Semiconductor Devices, 3rd Edition. Wiley Interscience, Hoboken, 2007.
[7] T. Y. Tseng and S. M. Sze, Nonvolatile Memories Materials, Devices, and Applications, American Scientific Publishers, Stevenson Ranch, 2012.
[8] International Technology Roadmap for Semiconductor, ITRS
http://www.itrs.net/ITRS%2019992014%20Mtgs,%20Presentations%20&%20Links/2013ITRS/2013Chapters/2013PIDS_Summary.pdf
[9] Yamauchi, N.; Hajjar, J.-J.J.; Reif, Rafael, "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," Electron Devices, IEEE Transactions on, vol.38, no.1, pp.55-60, Jan 1991.
[10] Tzu-Hsuan Hsu; Hang-Ting Lue; Erh-Kun Lai, et al., "A High-Speed BE-SONOS
NAND Flash Utilizing the Field-Enhancement Effect of FinFET," Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp.913-916, 10-12 Dec. 2007.
[11] Heyns, M.; Beckx, S.; Bender, H., et al., "Scaling of high-k dielectrics towards sub- 1nm EOT," VLSI Technology, Systems, and Applications, 2003 International Symposium on, pp.247-250, 2003.
[12] Chau, R.; Datta, S.; Doczy, M.; et al., "High-κ/metal-gate stack and its MOSFET characteristics," Electron Device Letters, IEEE, vol.25, no.6, pp.408-410, June 2004.
[13] Sheng-Chih Lai; Hang-Ting Lue; Ming-Jui Yang, et al., "MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation," Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE, pp.88-89, 26-30 Aug. 2007.
[14] Yan-Ny Tan; Chim, W.-K.; Jin Cho, et al., "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer,"Electron Devices, IEEE Transactions on, vol.51, no.7, pp.1143-1147, July 2004.
[15] Hang-Ting Lue; Szu-Yu Wang; Erh-Kun Lai, et al., "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," ElectronDevices Meeting, 2005. IEDM Technical Digest. IEEE International, pp.547-550, 5-5Dec. 2005.
[16] Ping-Hung Tsai; Kuei-Shu Chang-Liao; Tai-Yu Wu, et al., "Novel SONOS-type nonvolatile memory device with stacked tunneling and charge-trapping layers," Semiconductor Device Research Symposium, 2007 International, pp.1-2, 12-14 Dec. 2007.
[17] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al., "Nanowire transistors without junctions," Nat Nano, vol. 5, pp. 225-229, 2010.
[18] Colinge, J.P.; Lee, C.-W.; Afzalian, A., et al., "SOI gated resistor: CMOS without junctions," SOI Conference, 2009 IEEE International, pp.1-2, 5-8 Oct. 2009.
[19] Su, Chun-Jung et al. “A Junctionless SONOS Nonvolatile Memory Device Constructed with in Situ-Doped Polycrystalline Silicon Nanowires.” Nanoscale Research Letters 7.1 2012.
[20] Hang-Ting Lue; Yi-Hsuan Hsiao; Pei-Ying Du, et al., "A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance," VLSI Technology, 2009 Symposium on, pp.224-225, 16-18 June 2009.
[21] Zhang, Rui; Iwasaki, T.; Taoka, Noriyuki, et al., "High-Mobility Ge PMOSFET with 1-nm EOT Al2O3 / GeOx / Ge Gate Stack Fabricated by Plasma Post Oxidation,"Electron Devices, IEEE Transactions on, vol.59, no.2, pp.335-341, Feb. 2012.
[22] Weltzer, L.M.; Banerjee, S.K., "Enhanced CHISEL programming in flash memory devices with SiGe buried layer," Non-Volatile Memory Technology Symposium, 2004, pp.31-33, 15-17 Nov. 2004.
[23] Kencke, D.L.; Xin Wang; Ouyang, Q., et al., "Enhanced secondary electron injection in novel SiGe flash memory devices," Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International, pp.105-108, 10-13 Dec. 2000.
[24] Wolfson, S.C.; Fat Duen Ho, "Transient Simulation to Analyze Flash Memory Erase Improvements Due to Germanium Content in the Substrate," Electron Devices, IEEE Transactions on, vol.57, no.10, pp.2499-2503, Oct. 2010.
[25] Chi-Chao Wang; Kuei-Shu Chang-Liao; Chun-Yuan Lu, et al., "Enhanced Band-to- Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification," Electron Device Letters, IEEE, vol.27, no.9, pp.749-751, Sept. 2006.
[26] Li-Jung Liu; Kuei-Shu Chang-Liao; Yi-Chuen Jian, et al., "Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device with SiGe Buried Channel," Electron Device Letters, IEEE, vol.33, no.9, pp.1264-1266, Sept. 2012.
[27] Li-Jung Liu; Chang-Liao, Kuei-Shu; Yi-Chuen Jian, et al., "Enhanced programming and erasing speeds in p-channel charge-trapping flash transistor devices with SiGe channel," Semiconductor Device Research Symposium (ISDRS), 2011 International, pp.1-2, 7-9 Dec. 2011.
[28] B. Van Zeghbroeck, Principles of Semiconductor Devices. Boulder, CO: Univ.Colorado, 2007.
[29] Kuo-Nan Yang; Huan-Tsung Huang; Ming-Chin Chang, et al., "A physical model for hole direct tunneling current in p+ poly-gate pMOSFETs with ultrathin gate oxides," Electron Devices, IEEE Transactions on, vol.47, no.11, pp.2161-2166, Nov 2000
[30] Simon Tam; Ko, P.-K.; Chenming Hu, "Lucky-electron model of channel hot- electron injection in MOSFET'S," Electron Devices, IEEE Transactions on, vol.31, no.9, pp.1116-1125, Sep 1984.
[31] White, M.H.; Yang Yang; Ansha Purwar; French, M.L., "A low voltage SONOS nonvolatile semiconductor memory technology," Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, pp.52-57, 24-26 Jun 1996.
[32] W.J. Tsai; N.K. Zous; Liu, C.J., et al.., "Data retention behavior of a SONOS type two-bit storage flash memory cell," Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International, pp.32.6.1-32.6.4, 2-5 Dec. 2001.
[33] Ohnakado, T.; Mitsunaga, K.; Nunoshita, M., et al., "Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell," Electron Devices Meeting, 1995. IEDM '95., International, pp.279-282, 10-13 Dec 1995.
[34] Chun-Yuan Chen; Kuei-Shu Chang-Liao; Li-Jung Liu, et al., "Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device with SiGe Buried Channel," Electron Device Letters, IEEE, vol.35, no.10, pp.1025-1027, Oct. 2014.
[35] Sun, Y.; Yu, H.Y.; Singh, N.; et al., "Demonstration of memory string with stacked junction-less SONOS realized on vertical silicon nanowire," Electron Devices Meeting (IEDM), 2011 IEEE International, pp.9.7.1-9.7.4, 5-7 Dec. 2011.
[36] Sung-Jin Choi; Moon, Dong-Il; Duarte, J.P., et al., "A novel junctionless all-around- gate SONOS device with a quantum nanowire on a bulk substrate for 3D stack NAND flash memory," VLSI Technology (VLSIT), 2011 Symposium on, pp.74-75, 14-16 June 2011.
[37] Ko-Hui Lee; Horng-Chih Lin; Tiao-Yuan Huang, "A Novel Charge-Trapping-Type Memory with Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer,"Electron Device Letters, IEEE, vol.34, no.3, pp.393-395, March 2013.
[38] Zong-Hao Ye; Kuei-Shu Chang-Liao; Cheng-Yu Tsai; Tzu-Ting Tsai; Tien-Ko Wang, "Enhanced Operation in Charge-Trapping Nonvolatile Memory Device with Si3N4/Al2O3/HfO2 Charge-Trapping Layer," Electron Device Letters, IEEE, vol.33, no.10, pp.1351-1353, Oct. 2012
[39] Y. X. Liu, T. Mastukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, and M. Masahara, “Variability Analysis of Scaled Poly-Si Channel FinFETs and Tri-gate Flash Memories for High Density and Low Cost Stacked 3D-Memory Application,” in Solid-State Device Research Conference (ESSDERC), pp. 203-206, September 2011.
[40] Lu Zhang, Wei He, Daniel S. H. Chan, and Byung Jin Cho, “Multi-layer high-k Interpoly Dielectric for Floating Gate Flash Memory Devices,” in Solid State Electron, vol. 52, no. 4, pp. 564-570, April 2008.
[41] Jong Jin Lee, Xuguang Wang, Weiping Bai, Nan Lu, and Dim-Lee Kwong, “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device with HfO2 High-k Tunneling Dielectric,” in IEEE Trans. Electron Devices, vol. 50, no. 10, pp.2067-2072, October 2010.