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研究生: 羅哲偉
Che-Wei Lo
論文名稱: 多級架構之類似電路交換機
Multi-Stage Architecture for Quasi-Circuit Switch
指導教授: 蔡育仁
Ywh-Ren Tsai
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 通訊工程研究所
Communications Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 59
中文關鍵詞: 類似電路交換機布可荷夫-范紐曼交換機多層架構交換機傳輸速率保證封包延遲控制
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  • 在能夠控制封包延遲之情況下,我們將提出多級架構之類似電路交換機來進行討論。在輸入訊務符合峰值平穩 ((r, T)-smooth) 的限制條件之下,也就是在一定的時間區間之內,每一個流量的訊務量確保一定在某一個已知的最大訊務量之下。基於此種假設,增加一層負載平衡的 Birkhoff-von Neumann 類似電路交換機,可以達到傳輸速率保證的服務,也就是能夠控制封包的延遲時間。因為不會產生封包順序混亂的情形,此架構不需要在輸出端增加一個重新排序的暫存器。

    此類似電路交換的架構雖然可以達到傳輸速率保證的服務,但是當交換機的架構擴大時,其最大封包延遲時間也同時增加。同時,也提高了硬體設計的複雜度。為此,我們提出一個多級架構之類似電路交換機,以 Banyan 網路為基礎的系統,用多個硬體設計複雜度低的 類似電路交換機完成一個大的交換機網路。此架構同樣具有傳輸速率的保證。當中的每一個交錯式交換機的變更週期與碼框的大小相同,不需要做另外的計算以降低複雜度。我們將證明在交換機的架構大於 時,Banyan-based類似電路交換機相較於加一層負載平衡的Birkhoff-von Neumann 類似電路交換機,具有較低的最大封包延遲時間,與較佳的統計特性。與Benes類似類似電路交換機比較,我們可以證明在碼框小於某些邊界值時,Banyan-based類似電路交換機具有較低的最大封包延遲時間與平均封包延遲時間。


    In this thesis, we propose the multi-stage architecture for quasi-circuit switching to discuss. In the previous work, we have assumed that all input flows are (r, T)-smooth. Furthermore, it is assumed that the all inputs of an switch satisfy the no overbooking condition. Load balanced Birkoff-von Neumann quasi-circuit switch is one of quasi-circuit switches. It can provide guaranteed rate services and all the packets would be transmitted their destinations without lost.

    Although this quasi-circuit switch can offer quality of services, the maximum delay becomes larger and the hardware complexity increases as the size of switch fabric is large. Therefore, we propose a multi-stage architecture for quasi-circuit switch, called Banyan-based scheme. It is composed of some quasi-circuit switches. Each of crossbar fabrics has one-cycle permutation matrix and changes its matrix every frame time. We will prove that the Banyan-based scheme has less maximum delay than former scheme as the size of switch fabric is larger than . To compare with Benes quasi-circuit switches; the Banyan-based scheme has less maximum and average delay as the frame size is less than some values.

    1 Introduction 1 2 Related Principles of Packet Switches 3 2.1 Output-buffered switch and input-buffered switch 3 2.2 Head-of-line blocking and virtual output queueing 6 2.3 Load balanced Birkoff-von Neumann switches 8 3 Quasi-Circuit Switching 10 3.1 Definitions and basic properties 10 3.2 Load balanced Birkoff-von Neumann quasi-circuit switches 12 3.3 Benes quasi-circuit switches 16 4 Banyan-Based Quasi-Circuit Switches 19 4.1 New architecture based on banyan network 19 4.2 Banyan-based scheme with speed up 2 times 23 5 Discussions, Simulation & Numerical Results 35 5.1 Simulation and numerical results 35 5.2 Simulation results 37 5.2.1 Simulation results for Banyan-based scheme and frame based scheme 38 5.2.2 Simulation results for Banyan-based scheme and Benes scheme 48 6 Conclusions 57 Bibliography 58

    [1] C.-S. Chang and D.-S. Lee, "Quasi-circuit switching and quasi-circuit Switches," to be presented in Cheng-Shang Chang's home page.
    [2] C.-S. Chang, D.-S. Lee and C.-Y. Yue, "Providing Guaranteed Rate Services in the load balanced Birkhoff-von Neumann switches," in Proc. IEEE INFOCOM, pp. 1622-1632, 2003.
    [3] C.-S. Chang, W.-J. Chen and H.-Y. Huang, "Birkhoff-von Neumann input buffered crossbar switches," in Proc. IEEE INFOCOM, pp. 1614-1623, 2000.
    [4] C.-S. Chang, W.-J. Chen and H.-Y. Huang, "Birkhoff-von Neumann input buffered crossbar switches for Guaranteed-Rate Services," IEEE Transactions on Communications, vol. 49, pp. 1145-1147, July 2001.
    [5] C.-S. Chang, D.-S. Lee and Y.-S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," Computer Communications, vol. 25, pp. 611-622, 2002.
    [6] C.-S. Chang, D.-S. Lee and C.-M. Lien, "Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering," Computer Communications, vol. 25, pp. 623-634, 2002.
    [7] J. G. Dai and B. Prabhaker, “The throughput of data switches with and without speed up,“ Proc. IEEEINFCOM, pp. 556-564, Tel Aviv, Israel, Apr.2000.
    [8] S. J. Golestani, “Congestion-free communication in high speed packet networks,” IEEE Transactions on Communications, vol. 39, pp. 1802-1812, Dec. 1991.

    [9] Hung, G. Kesidis and N. McKeown, “ATM input-buffered switches with guaranteed-rate property,” Proc. IEEE ISCC’98, pp.331-335, 1998.
    [10] M. J. Karol, M. G. Hluchyj, and S.P. Morgan, “Input Versus Output Queueing on a Space-Division Packet Switch,” IEEE Trans. Communication, vol. 35, pp. 1347-1356, Dec. 1987.
    [11] N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,” IEEE Transactions on Networking, vol. 7, pp. 188-201, April 1999.
    [12] H. J. Chao, C. H. Lam and E. Oki, Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers. John Wiley & Sons, Inc., 2001.

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