電源電壓縮調技術，通常在低功耗系統級芯片（SoC）設計中被採用。但不利的影響對記憶體電路來說已日益顯著，如電壓相關的時序偏移和小感應電壓容許空間。在本論文中，我們對電壓相關的時序偏移和小感應電壓容許空間在記憶體電路所造成的功能故障進行了研究，並且提出了克服電壓相關的時序偏移與減少感應電壓容許空間需求的電路技術。
電壓相關的時序偏移常造成記憶體電路在預充電與感測階段的功能故障並造成記憶體電路在速度性能方面的下降。同時，儲存資料相關的位元線漏電流更進一步增加了時序偏移並降低記憶體存電路的良率。因此我們發展了Dual-Mode Self-Timed (DMST) 技術來消除時序偏移在不同製程,電壓與溫度 (PVT) 條件下所造成的功能故障與速度性能的損失。相較於傳統的位元線時序追踪技術，在相同的電路面積下，DMST技術，實現了高可擴展性和良好的減少時序偏移成果。實驗結果顯示，DMST技術可以在很寬的電源電壓範圍運作，從額定電壓 (VDD = 3.3V) 的39.4 ％到151.5 ％。
低的供應電源電壓已成為有效降低電路功率消耗的一種途徑。但這種方法常導致感應電壓容許空間縮小，並導致速度性能下降與記憶體電路讀取功能故障，特別是對於那些高密度優先的記憶體如被設計成長位元線以提高記憶位元陣列效率的單端讀取的NAND-ROM。這裡我們提出了Data-Aware Sensing Reference (DASR) 機制，它在給定的時序內維持讀0和讀1所需的感讀裕量。其中的關鍵機制在於採取自適變化的參考電壓的，使得所述的讀1和讀取0感應電壓容許空間相重疊，如同差動讀取的位元線組。實驗結果顯示90奈米CMOS邏輯製程所製作的256 Kb DASR NAND ROM 能在0.25 V的操作電壓下運作。同時在操作電壓=0.31V下, DASR較傳統NAND ROM的設計能增加66.7 ％的速度性能表現。
綜上所述，本論文所提出的DMST和DASR技術運用於記憶體電路以克服低功耗系統晶片在實現上所面臨的挑戰。

Supply-voltage (VDD) scaling techniques are often employed in low power Sys-tem-on-Chip (SoC) design; however, adverse impacts such as voltage-dependent timing skews and small sensing headroom have become increasingly significant on memory circuits. In this dissertation, functional failures induced by voltage-dependent timing skews and small sensing headroom in memory circuits are investigated. Techniques to overcome voltage-dependent timing skews and reduce sensing headroom requirement are proposed.
Voltage-dependent timing skews in precharge and sensing activities cause func-tional failure and reduce the speed performance of embedded memory. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of memory circuit. A dual-mode self-timed (DMST) technique is developed to eliminate the timing-skew-induced failures and speed degradation across various process, voltage and temperature (PVT) conditions. Comparing to the conventional sense-tracking-only replica column schemes, DMST technique achieves high scalability and timing skews reduction for various bitline (BL) lengths. Experimental results demonstrated that the DMST technique can operate continuously over a wide range of supply-voltage, from 39.4% to 151.5% of the nominal supply-voltage VDD = 3.3V.
Low supply-voltage has emerged as an effective way to reduce circuit power con-sumption. However, this approach incurs small sensing headroom which leads to speed performance degradation and read functional failure in memory circuits, particularly for those density-prioritized memories such as NAND-ROM using a longer single-ended BL sensing scheme to achieve high cell array efficiency. A data-aware sensing reference (DASR) scheme is proposed for maintaining sensing margins for both read-0 and read-1 under given timing constraints at low supply-voltage. The key mechanism involved in maintaining the read sensing margins is the adaptive changing of the reference voltage, such that the sensing headroom or potential range for read-1 and read-0 overlap, as in differential BL sensing. The fabricated 256 Kb DASR NAND-ROM macros in 90-nm bulk CMOS logic process are functional down to 0.25 V. DASR also increases the ac-cess speed by 66.7% at VDD = 0.31 V, compared with other conventional approach without the proposed DASR scheme.
In summary, the DMST and DASR techniques are proposed in this dissertation to deal with the challenging design obstacles in memory circuits for reliable low power SoC implementations.

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