晶圓廠在奈米晶圓上準確量測電容與電阻已有充分的經驗與可信的成果。由於互連 (Interconnect) 尺寸 (Dimension) 的縮小、銅製程技術的採用、SoC設計觀念的引進以及高頻晶片的需求大增，使得原本不被重視的寄生效應 (Parasitics)，如今卻因為超過八層、超過百萬條複雜互連的寄生效應，成為影響效能的重要因素之一。互連的寄生效應包括了寄生電阻、寄生電容以及寄生電感。由於互連尺寸降低與複雜度提高的影響，使得互連的電阻變大、電容變大、電感效應難以預測。其中，不論高頻抑或低頻晶片，寄生電容都深深地影響了晶片的效能表現 (Performance)。所以，如何有效並正確地估算複雜度提高的寄生電容 (Parasitic Capacitance)，成為一個能準確量測電容後仍值得注意的議題。

在這篇論文當中，除了簡介Raphael的基本原理外，並舉出其使用的例子，以及在Dummy Metal Fills與X-architecture方面的應用與問題。希望藉由這篇論文，能夠對於有效及正確使用Raphael抽取寄生電容，提供使用上的範例及正面的幫助系統晶片的設計。

Silicon foundries have had sufficient experiences and reliable results in silicon wafer measurements of nanometer interconnect capacitances and nanometer interconnect resistances. Technology has advanced from 180um, 130um, then into 90nm, with material migration from aluminum to copper as well. In addition to technology evolution, SoC and high-frequency design have been introduced for these years. Due to all the above plus more than eight metal layers and millions of interconnects in each system-on-chip (SoC), we have greater parasitic resistance, greater parasitic, more unpredictable inductance than before. As result, parasitics on interconnect becomes the first factor in performance of a chip. Further, parasitic capacitance highly affects performance either in high-frequency or in low-frequency chip. So, how to model parasitic capacitance efficiently and accurately is an issue now.

In the paper, there will be introduction to Raphael, then two simple examples for tutorial, and applications in x-architecture and dummy metal fills at last. And it will give advices and hints how to correlate parasitic capacitance accurately with silicon measurement to help SoC designs.

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