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研究生: 林餘德
Lin, Yu-Te
論文名稱: 具有針對向量最佳化之向量資料流分析之開放計算語言編譯器
An OpenCL Compiler Framework with Vector Data Flow Analysis for SIMD Optimizations on CPUs+GPUs
指導教授: 李政崑
Lee, Jenq-Kuen
口試委員: 游逸平
黃冠寰
許雅三
黃慶育
蘇泓萌
陳鵬升
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2016
畢業學年度: 104
語文別: 英文
論文頁數: 100
中文關鍵詞: 編譯器繪圖處理器向量運算向量語法分析資料流分析
外文關鍵詞: OpenCL compiler, GPU, SIMD optimization, vector parsing, data flow analysis
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  • 異質多核心平台已被廣泛的使用於嵌入式系統與高效能計算領域,由於異質多核心平台結合了多個不同架構的處理器於同一個平台,因此會需要非常先進的軟體開發框架來協助軟體的開發,Open Computing Language (OpenCL)為目前廣泛使用於異質多核心平台的軟體開發框架,在OpenCL的組成中,其後端編譯器扮演著非常重要的角色,它負責將使用者的程式編譯成支援多個不同架構處理器的執行檔,目前常見的OpenCL開發工具大多利用LLVM作為其後端編譯器,此現象衍生出一個有趣的問題:OpenCL是否可以在其他編譯器上被有效率的實作出來?在其他編譯器上實現OpenCL不論在學術研究上或是OpenCL本身的發展上可望帶來更多革新,此外OpenCL原生支援的向量運算亦使得編譯器需要不同於以往的資料流分析方法。

    此論文提出了一套在Open64編譯器上支援OpenCL的方法,Open64本身具備許多著名的最佳化技術,在Open64上支援OpenCL可使這些最佳化技術有機會被利用在OpenCL的程式上,此論文支援OpenCL的方法將涵蓋Open64編譯器的前端、中端與後端等重要部分,在實現OpenCL的支援後,我們亦在Open64上實現了支援OpenCL向量運算的資料流分析方法,並且基於此向量運算資料流分析方法更進一步的提出適用於OpenCL向量運算的編譯器最佳化技術。

    最後我們進行了一系列的實驗,實驗結果顯示,利用Open64所開發的OpenCL編譯器可成功編譯並執行多個來自AMD APP SDK的測試程式,而我們所提出的OpenCL向量運算編譯器最佳化技術,可於x86 CPUs與AMD GPUs的環境下分別帶來22%與4%的效能提升,此結果證明利用Open64作為一套OpenCL編譯器為一可行的方法,同時亦可利用Open64來開發OpenCL相關的編譯器最佳化技術。


    The use of heterogeneous multi-core platforms for both embedded and high-performance computing is becoming widespread. The integration of processors of different types means that these platforms require novel frameworks for supporting the development of software for them. Open Computing Language (OpenCL) is a commonly used framework for programming on heterogeneous multi-core platforms. One of the most important parts of OpenCL is the back-end compiler that compiles OpenCL programs for different processors. Most OpenCL compilers currently utilize LLVM as their compiler
    infrastructure, which presents an interesting question: Can OpenCL be effectively implemented on other compiler infrastructures? Supporting OpenCL on other compiler infrastructures could provide the opportunity to incorporate more academic innovations in the development of OpenCL and its applications. The support of single-instruction multiple-data (SIMD) linguistics of OpenCL also requires special compiler data flow analysis to meet the optimization requirements.

    Here we describe a method to apply an OpenCL compiler based
    on the Open64 compiler infrastructure to AMD graphics processing units (GPUs) and x86 CPUs. Open64 is equipped with many legacy compiler optimizations, supporting OpenCL on Open64 provides the potential for these legacy optimizations to be applied to OpenCL programs. The required procedures are detailed herein for the front-end, middle-end, and back-end of the Open64 compiler. We then propose a calculus framework to support the data flow analysis of vector constructs for OpenCL programs that compilers can use to perform SIMD optimizations. We model OpenCL vector operations as data access functions in the style of mathematical functions. We then show that the data flow analysis for OpenCL vector linguistics can be performed based on the data access functions. Based on the information gathered from data flow analysis, we illustrate a set of SIMD optimizations on OpenCL programs.

    Preliminary experimental results have demonstrated that the Open64-based OpenCL compiler can successfully compile fifteen benchmarks from the AMD APP SDK. Executing the compiled programs on the AMD GPU platform also produces correct results. The experimental results incorporating our calculus and our proposed compiler optimizations show that the proposed SIMD optimizations can provide average performance improvements of 22% on x86 CPUs and 4% on AMD GPUs. For the selected fifteen benchmarks, eleven of them are improved on x86 CPUs and six of them are improved on AMD GPUs. These results demonstrate the potential to adopt Open64 as an alternative OpenCL compiler as well as develop OpenCL SIMD optimizations on Open64.

    中文摘要iii Abstract v Acknowledgements vii 1 Introduction 1 1.1 OpenCL and compiler infrastructures . . . . . . . . . . . . . . . . . 1 1.2 Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Dissertation organization . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Background 9 2.1 OpenCL overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 OpenCL platform model . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 OpenCL execution model . . . . . . . . . . . . . . . . . . . . 10 2.1.3 OpenCL memory model . . . . . . . . . . . . . . . . . . . . . 11 2.1.4 OpenCL programming language . . . . . . . . . . . . . . . . 11 2.2 Open64 compiler infrastructure . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 Compiler front-end of Open64 . . . . . . . . . . . . . . . . . 14 2.2.2 WHIRL IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Code generator intermediate representation . . . . . . . . . . 16 2.3 The AMD GPU platform . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.1 AMD IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 Register swizzles . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.3 BIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Compiler for General-Purpose Computation on GPUs 21 3.1 Compiler overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Program transformation methodology . . . . . . . . . . . . . . . . . 23 3.3 Compiler implementation . . . . . . . . . . . . . . . . . . . . . . . . 25 4 OpenCL Compiler Design and Implementation 28 4.1 Compiler front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 Building tree nodes for OpenCL vector data types . . . . . . 29 4.1.2 Initializing vector variables . . . . . . . . . . . . . . . . . . . 31 4.1.3 Referencing vector components . . . . . . . . . . . . . . . . . 32 4.1.4 Parsing vector binary expressions . . . . . . . . . . . . . . . . 32 4.1.5 Address and function qualifier handling . . . . . . . . . . . . 35 4.2 Compiler middle-end . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 Lowering flow-control statements . . . . . . . . . . . . . . . . 37 4.2.2 Lowering direct load/store operations of OpenCL vectors . . 39 4.3 Compiler back-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.1 CGIR extension . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.2 Stack layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.3 Register allocation . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.4 Basic compiler optimizations . . . . . . . . . . . . . . . . . . 44 5 Data Flow Analysis of OpenCL Vectors 47 5.1 Motivating examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 Data access function of OpenCL vectors . . . . . . . . . . . . . . . . 51 5.3 Data flow analysis of data access functions . . . . . . . . . . . . . . . 54 5.3.1 Intersection of data access functions . . . . . . . . . . . . . . 55 5.3.2 Union of data access functions . . . . . . . . . . . . . . . . . . 57 5.3.3 Complement of data access functions . . . . . . . . . . . . . . 58 5.3.4 Canonicalization of data access functions . . . . . . . . . . . 60 5.3.5 Kill operation of data access functions . . . . . . . . . . . . . 61 6 Compiler Optimizations for OpenCL Vectors 62 6.1 Dependence analysis of OpenCL vectors . . . . . . . . . . . . . . . . 62 6.2 SIMD optimizations for OpenCL programs . . . . . . . . . . . . . . . 66 6.2.1 Vector aggregation . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.2 Vector copy propagation . . . . . . . . . . . . . . . . . . . . . 73 6.2.3 Vector common sub-expression elimination . . . . . . . . . . 76 7 Evaluations and Discussions 82 7.1 Correctness and basic performance evaluations . . . . . . . . . . . . 82 7.1.1 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1.2 Evaluation results . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 Experiments of the proposed OpenCL vector optimizations . . . . . 87 7.2.1 Experimental setup . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2.2 Performance results . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.3.1 Function inlining . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.3.2 Branch divergence . . . . . . . . . . . . . . . . . . . . . . . . 92 8 Conclusion 94 Bibliography 96

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