簡易檢索 / 詳目顯示

研究生: 許碩祐
Hsu, Shuo-You
論文名稱: 機器學習技術應用於系統性製程變異特徵之辨認方法
Feature Identification of Systematic Process Variations with Machine Learning Techniques
指導教授: 劉靖家
Liou, Jing-Jia
口試委員: 張克正
Chang, Keh-Jeng
陳竹一
Chen, Jwu E
劉靖家
Liou, Jing-Jia
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 81
中文關鍵詞: 超大型積體電路系統性製程變異機器學習
外文關鍵詞: VLSI circuits, Systematic Process Variations, Machine Learning
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨著互補式金屬氧化物半導體製程技術進入深次微米時代,製程變異對於產品良率影響越趨嚴重。為了辨認製程變異不確定性所造成的低良率原因,製程監控電路,例如: 環型震盪器、延遲鏈或者是以延遲錯誤測試為基礎的診斷方法被應用於量測晶片因為製程變異所引起的額外元件延遲。依據所量測到的元件延遲資訊,本論文提出了一套方法進一步地區分不同的製程變異所造成的影響並辨認引起製程變異的主要設計特徵 (即最有可能引起製程變異的原因,例如:邏輯閘種類)。此結果可以回饋給電路設計者與製程工程師,進而快速修正電路設計或調整製程參數以克服製程變異所造成的影響且有效地提升產品的良率。

    在本論文中,我們提出一套自下而上 (bottom-up) 分析方法,首先將晶片依據實體位置切分成數個子區塊。使用支持向量回歸法 (support vector regression) 建構製程變異模型,並逐步地合併子區塊如果製程變異的行為可以被相同製程變模型所解釋,此方法可以有效的區分不同製程變異的影響與其影響的範圍。而後,使用機器學習領域中的特徵萃取演算法分析並排序電路的特徵。越高排序的特徵代表越有可能是引起製程變異的主要原因。

    實驗結果顯示,本論文所提出的方法可以有效地辨認不同的製程變異影響區域並且能找出引起製程變異的主要特徵。


    As the CMOS technology coming to nano meter scale, process variation play an important role in yield of production. In order to identify variability issues for low yield process, process monitoring circuitry, such as ring oscillators, delay chain, or delay-test-based diagnosis methods are applied to measure excessive delays in a circuit. Based on the observed delay data, we propose to further classify and find the main features (most possible causes, e.g., gate types) that would explain the severity of a particular process region. Then fed back information to designers and process engineers. That can help them rapidly tune design or adjust process parameter to overcome the issue caused by process variation and promote the yield of production.

    In our method, support vector regression is employed to build models and partition the circuit into different process regions. That can distinguish different process variation influence and its affected regions. Then feature extraction algorithm in machine learning field is applied to rank features. The feature with higher rank, means it have more probability to cause process variation.

    Experimental results show that the proposed method can effectively identify process regions and rank injected variations.

    1 Introduction 9 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Preview of Systematic Variation Feature Identification Method . . . . . . . . . . . 11 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Background and Reviews of Previous Works 13 2.1 Process Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Machine Learning Techniques applied on VLSI Diagnosis . . . . . . . . . . . . . 15 2.3 Delay Fault Diagnosis Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Distinguish Chip Region Affected by Systematic Process Variation 20 3.1 Generate Delay Variation Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Excess Delay Contour and Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 Generate Layout Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Search and Merge Feasible Partitions . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 Analyze and Generate Process Models . . . . . . . . . . . . . . . . . . . . . . . . 32 4 Feature Extraction for Systematic Process Variation 33 4.1 Feature Selection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.1 Fisher Score . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.2 Linear Support Vector Machine Weights . . . . . . . . . . . . . . . . . . . 36 4.2 Feature Identification of Systematic Process Variation . . . . . . . . . . . . . . . . 39 5 Implements and Experimental Results 41 5.1 Implement Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 Process Variation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.1 Two Dimensional Gaussian Process Variation Model . . . . . . . . . . . . 44 5.2.2 Lithography Simulation Process Variation Model . . . . . . . . . . . . . . 44 5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.1 Setup of Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.2 Single Design Feature Injection and Experimental Result . . . . . . . . . . 47 5.3.3 Multiple Design Feature Injection and Experimental Result . . . . . . . . . 57 5.3.4 X-Coma Lens Aberration Process Model and Experimental Result . . . . . 71 6 Conclusions and Future Work 77 6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

    [1] V. Mehrotra, Modeling the effects of systematic variation on circuit performance, PhD thesis,
    Dept. EECS, Massachusetts Institute of Technology, 2001.
    [2] R. Chang, Y. Cao, and C. J. Spanos, “Modeling the electrical effects of metal dishing due to
    cmp for on-chip interconnect optimization”, IEEE Transactions on Electron Devices, vol. 51,
    no. 10, Oct. 2004.
    [3] Y.-Y. Chen and J.-J. Liou, “A non-intrusive and accurate inspection method for segment delay
    variabilities”, Proceedings of IEEE Asian Test Symposium, 2009.
    [4] M. Nourani and A. Redhakrishnan, “Modeling and testing process variation in nanometer
    cmos”, Proceedings of IEEE International Test Conference, 2006.
    [5] A. Bassi, A. Veggetti, L. Croce, and A. Bogliolo, “Measuring the effects of process vari-
    ations on circuit performance by means of digitally-controllable ring oscillators”, Interna-
    tional Conference on Microelectronic Test Structures, 2003.
    [6] D. Boning, T. Maung, J. Chung, K.-J. Chang, and S.-Y. Oh an D. Bartelink, “Statistical
    metrology of interlevel dielectric thickness variation”, Proceedings of SPIE, 1994.
    [7] D. Boning and J. Chung, “Statistical metrology: understanding spatial variation in semicon-
    ductor manufacturing”, Proceedings of SPIE, 1996.
    [8] L.-C Wang, P. Bastani, and M. S. Abadir, “Design-silicon timing correlation-a data mining
    perspective”, Proceedings of Design Automation Conference, 2007.
    [9] P. Bastani, Nick Callegari, L.-C. Wang, and M. S. Abadir, “An improved feature ranking
    method for diagnosis of systematic timing uncertainty”, IEEE International Symposium on
    VLSI Design, Automation and Test, 2008.
    [10] P. Bastani, Nick Callegari, L.-C. Wang, and M. S. Abadir, “Diagnosis of design-silicon tim-
    ing mismatch with feature encoding and importance ranking – the methodology explained”,
    Proceedings of IEEE International Test Conference, 2008.
    [11] M. Sharma, B. Benware, L. Ling, D. Abercrombie, L. Lee, M. Keim, H. Tnag, W.-T. Cheng,
    T.-P. Tai, Y.-J. Change, R. Lin, and A. Man, “Efficiently performing yield enhancements by
    identifying dominant physical root cause from test fail data”, Proceedings of IEEE Interna-
    tional Test Conference, 2008.
    [12] K. Agarwal and S. Nassif, “Characterizing process variation in nanometer cmos”, Proceed-
    ings of Design Automation Conference, 2007.
    [13] B. Zhou and A. Khouas, “Measurement of delay mismatch due to process variations by means
    of modified ring oscillators”, Proceedings of International Symposium on Circuits and Sys-
    tems, 2005.
    [14] Alex J. Smola and Bernhard Scholkopf, “A tutorial on support vector regression”, Tech. Rep.,
    STATISTICS AND COMPUTING, 2003.
    [15] C.-W. Hsu, C.-C. Chang, and C.-J. Lin, “A partical guide to support vector classifi-
    cation”, 2009, Document available at http://www.csie.ntu.edu.tw/˜cjlin/papers/
    guide/guide.pdf.
    [16] Isabelle Guyon and Andr’e Elisseeff, “An introduction to variable and feature selection”, J.
    Mach. Learn. Res., vol. 3, pp. 1157–1182, Mar. 2003.
    [17] B. E. Boser, I. Guyon, and V. Vapnik, “A training algorithm for optimal margin classifier”,
    Proceedings of the Fifth Annual Workshop on Computational Learning Theory, pp. 144–152,1992.
    [18] Alain Rakotomamonjy, Isabelle Guyon, and Andre Elisseeff, “Variable selection using svm-
    based criteria”, 2003.
    [19] Y.-W. Chang and C.-J. Lin, “Feature ranking using linear SVM”, JMLR: Workshop and Con-
    ference Proceedings, 2008.
    [20] I. Guyon, J. Weston, S. Barnhill, and V. Vapnik, “Cancer classification using support vector
    machines”, Machine Learning Journal, vol. 46, pp. 389–422, Jan. 2002.
    [21] Chih-Chung Chang and Chih-Jen Lin, LIBSVM: a library for support vector machines, 2001,
    Software available at http://www.csie.ntu.edu.tw/˜cjlin/libsvm.
    [22] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda,
    “Statistical delay computation considering spatial correlations”, Proceedings of Asia & South
    Pacific Design Automation Conference, 2003.
    [23] K.-M. Chang, “Analysis of systematic variation for path delay and cirtical area with lithogra-
    phy simulation”, Master’s thesis, EE Dept., National Tsing-Hua University, Jan. 2009.
    [24] M.-C. Wu, “An aerial image simulator for fast critical dimension estimatoin of lithography
    process”, Master’s thesis, EE Dept., National Tsing-Hua University, Jan. 2008.
    [25] J. W. Goodman, Introduction to Fourier Optics, Roberts & Co, Englewood, Colo., 2005.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE