隨著DRAM(dynamic random access memories)記憶密度的增加，單位記憶胞的大小也越來越小。而電子陶瓷薄膜因具有高介電常數，可以降低記憶胞之面積，故受到相當的矚目。其中之(Ba,Sr)TiO3(BST)由於具有高介電常數、低漏電流、高崩潰電場、室溫下是順電相、以及容易控制成分等優點，極具潛力成為下世代DRAN之記憶材料。
在之前文獻報告中提到當以Ir為下電時極，BST具有較高之介電常數，其原因和退火後IrO2在BST及Ir界面生成有關。本論文研究即在高的Ar/O2混和氣壓下，在Ir下電極上鍍製BST，希望能在不需退火的情形下，在界面處自然會生成IrO2來提高介電常數。實驗結果發現當製成溫度為550℃時，初鍍膜之介電常數可達926，但相對的漏電流卻略顯過大。為了改善此現象，我們在純Ar氣氛下於Ir上先長一層薄的BST，來抑制IrO2過量成長所造成的表面粗糙度化，之後再以混和氣氛鍍製BST。此種雙層結構可減少IrO2形成量，降低表面粗糙度，達到高介電常數及低漏電流之高密度記憶材料之需要。

The advancement of dynamic random access memories (DRAM's) has significantly decreased the available area per cell. Electroceramic thin films with high dielectric constant have attracted great attention for practical use in capacitors of gigabit DRAM's since the adoption of high-dielectric-constant materials can lower the height of the storage node and simplify the cell structure. One of the most promising materials for the capacitor dielectric films is (Ba,Sr)TiO3 (BST) because of its high dielectric constant, low leakage current density, high dielectric breakdown strength, paraelectric perovskite phase that does not exhibit fatigue, and the ease of composition control due to the absence of volatile lead oxide.
The literature indicate the bottom electrode effects greatly the electric properties of BST. After annealing at 600~700℃ the BST with the bottom electrode of Ir possesses higher dielectric constant due to the IrO2 formation at the BST/Ir interface. To enhance the dielectric constant of BST without annealing process, the BST film were sputtered on the electrode of Ir under high working pressure of mixing Ar/O2 gas in this research. In the condition, the thin film of IrO2 was formed simultaneously at the interface between the BST and Ir films during the BST-deposited process. The best dielectric constant can achieve 926 at 550℃, but the leakage current is very poor. Finally, we apply the double BST layers, which was sputtering with pure Ar and mixing Ar/O2 gas, can not only have large dielectric constant but also have low leakage current.

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