此篇論文的研究主題為具矽奈米晶體之環繞式閘極複晶矽奈米線快閃記憶體，主要應用於3D堆疊結構的非揮發性記憶體。論文中使用矽奈米晶體為電荷儲存層以增加記憶體的可靠度；採多條環繞式閘極之奈米線結構增強穿遂氧化層電場，一方面提升寫入和抹除資料的效率，另一方面抑制電子從閘極注入減慢抹除速度。使元件擁有在高溫 (85oC) 下極佳的資料保持能力、良好的重複讀寫忍受度。綜合以上論述，具矽奈米晶體之環繞式閘極複晶矽奈米線快閃記憶體為一高效能且具有良好元件可靠度之非揮發性記憶體。
3D立體堆疊結構有利於電晶體尺寸的微縮，進而有效提高積體電路元件的密度與增加晶片的功能與設計彈性。氮化矽常被應用於浮停閘極結構的非揮發性記憶體中，由於氮化矽儲存層之中，矽奈米晶體所儲存的電荷更為集中，有利於元件重複讀寫的忍受度。且因為矽奈米晶體與氧化矽的傳導帶差值大於氮化矽與氧化矽的傳導帶差值，所以更增加此元件資料保持能力。同時，矽奈米晶體為離散的缺陷，二位元操作可以實現。靠著環繞式閘極與矽奈米晶體的特性，增強閘極控制能力，達到加速資料的寫入及抹除，論文中的實驗數據證明了此特性。
在論文列出此結構的各項可靠度指標，以及實驗數據皆顯示出具矽奈米晶體之環繞式閘極複晶矽奈米線快閃記憶體具有應用於實際產品的高度價值，同時擁有成為下一世代快閃記憶體的潛力。

This thesis research topics for the Nonvolatile memory (NVM) that is based on a structure of Gate-All-Around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) structure with Silicon-Nanocrystals (NCs) as the storage nodes is demonstrated. The GAA poly-Si-SiO2-Si3N4-SiO2-poly-Si (SONOS) NVMs are also fabricated and compared. Using 3-D multi-gate structure can increase the coupling-ratio, so fast program and erase speed can be obtained. Silicon-Nanocrystals charge trapping layer improved reliability in this work. Used the Gate-All-Around structure of the nanowires to enhance the tunneling oxide electric field, to increase the program and erase operation efficiently. On the one hand, to suppress the gate injection to avoid that slow erase speed. in the stacked structure of the non-volatile memory primarily. The GAA NCs NVMs have a 4.2 V of threshold voltage shift at 18 V for 1 ms, and are faster than the GAA SONOS NVMs do. In reliability studies, this NVM shows superior endurance after 104 program/erase (P/E) cycles, and loses only 14% of its charges lose after 10 years at 85 oC.
3D stacked structure can push flash memory device scaling down, and improve the high-density of integrated circuit effectively. Silicon nitride is often used in floating gate structure in non-volatile memory. Because the stored charge is concentrate in trapping layer with Silicon-Nanocrystals, it would improve device endurance. The difference conduction band between Silicon-Nanocrystals and silicon oxide would be enlarger, so it has increased the data retention of this element information. Silicon-Nanocrystals can display 2-bit operation due to its discrete trap, enhance gate control ability for increasing program and erase operation. The experimental data proved in thesis of this feature.
This work shows experimental data for device’s reliability, all the data can display Gate-All-Around Poly-Silicon Nanowires Flash Memory with Silicon-Nanocrystals has applied to high value actually, it would become the next-generation flash memory.

Chapter 1
[1-1]. Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti “Introduction to Flash Memory,” Proc. IEEE 91, 489–502, 2003.
[1-2]. D. Kahng and S. M. Sze, Bell Syst. Tech. J. 46, 1288, 1967.
[1-3]. Kahng D. and Sze S.M., “A floating gate and its application to memory devices”. Bell Syst. Tech. J. 46, pp.1288, 1967.
[1-4]. Harai E., Schmitz L., Troutman B., and Wang S., “A 256 bit nonvolatile static RAM”. IEEE ISSCC TECH. Dig., pp.108, 1978.
[1-5]. Kynett V.N., Baker A., Frandrich M., Hoekstra G.,Jungroth O., Kreifels J., and Wells S., “ An in-system reprogrammable 256K CMOS Flash memory”, ISSCC Tech. Dig., pp.132, 1988.
[1-6]. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Cheng-Wei Chou Yuan-Chun Wu, Hun-Hao Tu, and Chun-Yen Chang, “TNANO High-Performance Metal-Induced Lateral-Crystallization Polysilicon Thin-Film Transistors With Multiple Nanowire Channels and Multiple Gates,” IEDM Tech. Dig., 2006.
[1-7]. Navab Singh, Kavitha D. Buddharaju, S. K. Manhas, A. Agarwal, Subhash C. Rustagi, G. Q. Lo, N. Balasubramanian, and Dim-Lee Kwong, “Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications,” IEEE Transactions on Electron Devices,
vol. 55, No. 11, pp. 3107, 2008.
[1-8]. Po-Chun Huang, Lu-An Chen, and Jeng-Tzong Sheu, “Electric-Field Enhancement of a Gate-All-Around Nanowire Thin-Film Transistor Memory,” IEEE Electron Device Letters, vol. 31, No. 3, pp.216, 2010.

[1-9]. J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, “Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell,” IEEE Electron Device Letters, vol. 29, No. 5, pp. 518, 2008.
[1-10]. J.Fu, Y. Jiang, N. Singh, C. X. Zhu, G. Q. Lo, and D. L. Kwong, “Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture,” IEEE Electron Device Letters, vol. 30, No. 3, 2009.
[1-11]. Shih-Ching Chen, et al., “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,” Applied Physics Letters, 90, 122111, 2007.
[1-12]. Tsung-Yu Chiang, Tien-Sheng Chao, Yi-Hong Wu, and Wen-Luh Yang, “High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals,” IEEE Electron Device Letters, vol. 29, No. 10, pp. 1148, 2008.
[1-13]. Mei-Chun Liu, et al., “SONOS memories with embedded silicon nanocrystals in nitride,” Semicond. Sci. Technol., 23, 075033, 2008.
[1-14]. Tsung-Yu Chiang, et al., “Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals,” IEEE Trans. Electron Devices, vol. 57, NO. 8, 2010.
[1-15] Y. C. Wu, T. C. Chang, P. T. Liu, C. W. Chou, Y. C. Wu, C. H. Tu, and C.Y. Chang, “High-Performance Metal-Induced Lateral-Crystallization Polysilicon Thin-Film Transistors With Multiple Nanowire Channels and Multiple Gate,” IEEE Transactions on Nanotechnology, vol. 5, 157, 2006.

Chapter 2
[2-1] T. Y. Chan, K. K. Young, C. Hu, “A True Single Transistor Oxide-Nitride- Oxide EEPROM”, IEEE Electron Device Letters, EDL-8, No- 3, pp. 93-95, 1987.
[2-2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview,” Proceedings of IEEE, vol. 85, pp. 1248, 1997.
[2-3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, ch. 3, p.59, 1991.
[2-4]. Stanley Wolf, Silicon Processing for The VLSI ERA, vol.3, pp.435.
[2-5]. M. Lenzlinger, “Fowler-Mordheim Tunneling in thermal grown SiO2”, Appl. Phys. Lett., vol. 40, pp. 278-283, 1969.
[2-6]. P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-State Circuits, vol. 14, pp. 442, 1979.
[2-7]. I. C. Chen, C. Kaya and J. Paterson, “Band-to-band tunneling induced substrate
hot-electron (BBISHE) injection: A new programming mechanism for nonvolatile
memory devices,” IEDM, pp.263, 1989.
[2-8]. K. Tamer San, Cetin Kaya, and T. P. Ma, “Effects of Erase Source Bias On Flash EPROM Device Reliability”, Transactions on Electron Devices, vol. 42, pp.150, 1995.
[2-9]. Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Viscontio, “Introduction to Flash memory,” Proceedings of the IEEE, vol. 91, pp.489,2003.
[2-10]. P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mechanisms of Flash cell in program/erase cycling,” IEDM Tech. Dig., pp. 291–294, 1994.
[2-11]. Roberto Bez, Emilic Camerlenghi, Alberto Modelli, and Angelo Visconti,
“Introduction to Flash Memory,” Proc. IEEE, vol. 91, pp. 489-502, 2003.

Chapter 3
[3-1] G. Gay, et al., “Passivated TiN nanocrystals/SiN trapping layer for enhanced erasing in nonvolatile memory,” Appl. Phys. Lett., vol. 97, pp. 152112, 2010.
[3-2] Tsung-Yu Chiang, et al., “Characteristic of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals,” IEEE Transactions on Electron Devices, vol. 57, NO.8, 2010.