As the rapid growth of the mobile devices and the related marketplace, the embedded multicore systems are playing increasingly important role for consumer electronic design. The application developers for such systems try to optimize the designs for both performance and power consumption. Power consumption is especially the major concern because the battery sustain has an significant influence of product quality. However, the popular application design platforms such as QEMU and SID have no power metrics support to help developers optimize their design for power consumption. In this work, we design and implement a power aware simulation framework on embedded heterogeneous multicore system based on SID simulation framework. It is a high level simulation environment which provides full system simulation with timing information and also power estimation results for the target simulation applications. The proposed multicore simulator includes two major processor units, AndesCore and PAC DSP, which are both ingenious IP design from Taiwan Star IP program. The simulator also includes the memory subsystems, interconnection, DMA and other peripherals, which provide the full system simulation for multicore embedded application development. The power estimation flow for the proposed simulator containing two stages, IP level power modeling and system level power profiling. In the first stage, we build up the power estimation models for major IPs such as MPU ,DSP, memory subsystems, interconnection, and DMA. In the second stage, the IP power models are integrated into a power estimation module which connects to the simulator and generates the power profiling result according to the execution trace provided by simulator. In the experiments, DSP programs with SIMD intrinsics for DSPStone benchmark are examined. Also the face detection application is developed as a running example on the multicore system to show the power profiling result. Furthermore, an FIR program is presented to demonstrate the power optimization with DVS technique. The proposed simulation framework can help collaborate with developers in the optimization process to illustrate the view of power dissipation of the applications. Application developers benefit from the proposed simulation framework to verify their design and also help tune both performance and power consumption. In addition, we build up the simulation and power estimation tools to support ingenious design of Taiwan domestic IPs (such as PAC DSP and AndesCore) which can be added value of those IPs.

近年來，隨著手持式裝置及相關產業市場的蓬勃發展，嵌入式多核心系統在其中扮演的角色越來越重要。對於在此環境下開發應用程式的程式設計者而言，程式的效能及節能性是兩個重要的設計依據。依靠電池為電力來源的手持式裝置，產品對於節能的需求更高，也因此對於耗能的最佳化是此環境上程式設計不可或缺的步驟。然而，目前廣泛應用的高層級嵌入式系統程式開發平台，例如QEMU或SID，僅提供程式驗證及效能報告，對於耗能並沒有提供相關工具輔助程式開發者達到節能最佳化。因此，本論文設計並實作了高層級嵌入式多核心模擬器，並在此平台上提供耗能估測工具。此模擬器以SID模擬環境為架構，模擬完整的嵌入式系統環境，其上包含兩種主要的核心處理單元，分別為微處理器(AndesCore)和數位訊號處理器(PAC DSP)，除此之外，系統組成元件如記憶體、計時器、橋接線路及其他周邊設備等皆包含其中，提供程式開發者完整的系統模擬平台。於此平台上，我們建立了耗能估測工具以提供使用者程式耗能資訊。耗能估測工具的建構包含兩個步驟，其一為各元件的耗能模組建立。此步驟中，我們針對環境中重要的能量消耗元件，分析其特性建立個別的耗能模組。第二步驟中，已建立好的耗能模組被整合成一獨立的系統耗能估測計算模組，此模組與模擬平台連接，在模擬平台執行過程中，依照模擬器執行之數據計算出估測的耗能報告。本論文的實驗中，我們針對三組不同的測試程式展示耗能量測結果，分別為DSPStone Benchmark、人臉辨識演算法、無限脈衝響應濾波器。實驗中我們分析耗能估測工具對於程式開發者於單一元件、多核心環境上之元件耗能平衡最佳化、以及耗能及效能之間的取捨皆有幫助。本論文所建立的模擬平台及耗能估測工具可提供程式開發者驗證程式、並對效能及耗能作最佳化。除此之外，此一平台支援本土IP如AndesCore及PAC DSP，可提升其產品之附加價值。

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