在現今的晶片製造中，為了達成高速、高資料通道數、低功耗、小尺寸和異質整合等優點，所以將藉由使用如『矽載板中介層』 (Interposer)或『晶圓級封裝』(Wafer-Level Packaging)等整合技術來將多塊裸晶進行堆疊而形成多裸晶整合晶片。其中，此類型的晶片中的連接線也會由許多不同的材料構成而變得相當複雜，也因此這些連接線非常有機會因為早夭期失效或老化效應而變得脆弱不堪。為了提高晶片製造的良率與可靠度，在我們前一項作品中[12]提供了一個線上監測方法，此方法透過將連接線末端的轉態時間進行分類的流程來進行非侵入式地監測『穿矽連接孔』 (Through-Silicon Via)上的訊號傳遞延遲時間。但是，此方法並不適合應用於存在矽載板中介層或是晶圓級封裝晶片上的『連接線重新分配層』(Re-Distributed Layer, RDL) 中的長距離連接線上，因為此情況下會產生巨大的額外面積花費使其成本過於高昂。為了克服這項限制，我們在這篇論文中藉由納入一個『分散式時間至數位碼轉換器』(Distributed Time-to-Digital Converter, d-TDC) 而提出了一個新的方案。在此方案中，我們所提出的『分散式時間至數位碼轉換器』將會取代前一個作品中的脈衝寬度分類流程之階段，而直接將脈衝寬度上的時間資訊轉換成數位碼後輸出。實驗結果指出此種方案能夠支援長距離連接線的線上延遲時間監測，同時對於各個連接線所產生的額外面積花費相當於兩個邊界掃描電路的大小。

Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this thesis by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.

[1] T. Frank, S. Moreau, C. Chappaz, L. Arnaud, P. Leduc, A. Thuaire, and L. Anghel, "Electromigration Behavior of 3D-IC TSV Interconnects", Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp.326-330, June 2012.
[2] T. Frank, C. Chappaz, P. Leduc, L. Arnaud, F. Lorut, S. Moreau,A. Thuaire, R. El Farhane, and L. Anghel, “Resistance Increase Due to Electromigration Induced Depletion under TSV", Proc. of IEEE Int'l Reliability Physics Symp. (IRPS), pp. 3F.4.1-3F.4.6, April 2011.
[3] K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. S.Ho, “Thermal Stress Induced Delamination of Through Silicon Vias in 3D Interconnects," Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp. 40-45, June 2010.
[4] P. Lall, K. Mirza, and J. Shuling, "Damage Pre-Cursor Based Life Prediction of the Effects of Mean Temperature of Thermal Cycle on the SnAgCu Solder Joint Reliability," Proc. of Electronic Components and Technology Conf. (ECTC), pp. 990-1003, 2014.
[5] C.Serafy and A. Srivastava, "Online TSV Health Monitoring and Built-In Self-Repair to Overcome Aging", Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 224-229, 2013.
[6] L. Jiang, F. Ye, Q. Xu, K. Chakrabarty, and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs," Proc. of Design Automation Conf, pp. 1-6, 2013.
[7] K. Chakrabarty, “TSV Defects and TSV-Induced Circuit Failures: The Third Dimension in Test and Design-for-Test”, Proc. of Int’l Reliability Physics Symp., (IRPS), pp. 5F1.1-5F.1.12, 2012.
[8] Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[9] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[10] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits:Characterization, Test, and Optimal Spare Allocation”, Proc. of Design Automation Conf., pp. 10240-1030, June 2012.
[11] S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 8, pp. 1258-1268, Aug. 2014.
[12] S.-Y. Huang, H.-X. Li, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs", Proc. of Asian Test Symp. (ATS), pp. 162-167, Nov. 2014.
[13] J. Carretero, X. Vera, P. Chaparro, and J. Abella, “Microarchitectural Online Testing for Failure Detection in Memory Order Buffer”, IEEE Trans. on Computers, Vol. 59, No. 5, pp. 623-637, 2010.
[14] Y. Li, Y. M. Kim, E. Mintarno, D. S. Gardner, and S. Mitra, “Overcoming Early-Life Failure and Aging for Robust Systems,” IEEE Design & Test of Computers, Vol. 26, No. 6, pp. 28-39, 2009.
[15] T. H. Kim, R.Persaud, and Chris H. Kim. "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 874-880, 2008.
[16] S. L. Wright, et al, "Characterization of Micro-bump C4 Interconnects for Si-Carrier SOP Applications," Proc. of Electronic Components and Technology Conf.,pp. 633-640, 2006.
[17] S. L. Wright, et al, "Micro-interconnection Reliability: Thermal, Electrical and Mechanical Stress", Proc. Electronic Components and Technology Conf., pp. 1278-1286, May 2012.
[18] P. Chen, S.-I. Liu, and J. Wu, “A CMOS Pulse Shrinking Delay Element for Time Interval Measurement,” IEEE Trans. on Circuit and System II, vol. 47, no. 9, pp. 954-958,Sept. 2000.
[19] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.