This paper presents a statistic-based method to estimate testability of a design at
Register-Transfer Level (RTL). This testability estimation technique is composed of
a new high-level design representation and a Monte Carlo simulation which exploits
random pattern simulation and a statistic model for improving the error rate and
condence level. We conduct the experiments on a set of ISCAS'89 benchmarks and
some practical designs. The experimental results show that the proposed method is
promising in estimating testability at high-level design description. Thus, designers
can identify most hard-to-test points of a design prior to the synthesis task.

本論文提出一個以統計為基礎的方法來計算出暫存器轉換層級之設計的可測度。這個可測度分析的方法是由新的高階設計表示法和蒙特卡羅模擬所組成，透過隨機取樣模擬和統計模型的配合以改進誤差值和增加信心水準。我們的實驗是由一系列ISCAS'89設計和一些實際設計案例來當作測資。實驗結果指出我們提出的方法能有效的在高階設計中估計出可測度。因此程式設計師可以在電路合成之前先找出設計中可測度很低的點。

[1] V. D. Agrawal and S. C. Seth, \Probabilistic testability," in Proc. International
Conference on Computer Design, pp. 562{565, 1985.
[2] F. Brglez, \On testability of combinational networks," in Proc. International
Symposium on Circuits and Systems, pp. 221{225, 1984.
[3] J. D. Calhoun and F. Brglez, \A framework and method for hierarchical test
generation," in Proc. International Test Conference, pp. 480{490, 1989.
[4] V. Chaiyakul and D. D. Gajski, \Assignment decision diagram for high-level
synthesis," University of California, Irvine, Department of Information and
Computer Science, Technical Report ICS-TR-92-103, Dec. 1992.
[5] S. C. Chang, W. B. Jone, and S. S. Chang, \Tair: Testability analysis by implication
reasoning," IEEE Trans. Computer-Aided Design of Integrated Circuits
and Systems, pp. 152{160, Jan. 2000.
[6] C.-C. Chiou, C.-Y. Wang, and Y.-C. Chen, \A statistic-based approach to
testability analysis," in Proc. International Symposium on Quality Electronic
Design, pp. 267{270, 2008.
[7] L. H. Goldstein and E. L. Thigpen, \Scoap: Sandia controllability/observability
analysis program," in Proc. Design Automation Conference, pp. 190{196, 1980.
[8] Y. Huang, N. Mukherjee, W.-T. Cheng, and G. Aldrich, \A rtl testability
analyzer based on logical virtual prototyping," in Proc. Asian Test Symposium,
pp. 121{124, 2007.
36
[9] S. K. Jain and V. D. Agrawal, \Statistical fault analysis," IEEE Design & Test
of Computers, vol. 2, pp. 38{44, Feb. 1985.
[10] I. R. Miller, J. E.Freund, and R. Johnson, \Probability and statistics for engineers,"
Englewood Clis, NJ: Prentice Hall, 1990.
[11] C. P. Ravikumar and G. S. Saund, \A stafan-like functional testability measure
for register-level circuits," in Proc. Asian Test Symposium, pp. 192{198, 1995.
[12] J. Savir, G. S. Ditlow, and P. H. Bardell, \Random pattern testability," IEEE
Trans. Computers, pp. 79{90, Jan. 1984.
[13] S. C. Seth, L. Pan, and V. D. Agrawal, \Predict: Probabilistic estimation of
digital circuit testability," in Proc. Fault Tolerant Computing Symposium, pp.
220{225, 1985.
[14] J. Strnadel, \Testability analysis and improvements of register-transfer level
digital circuits," Computing and Informatics, pp. 1001{1024, Sep. 2006.
[15] M. Takahashi, R. Sakurai, H. Noda, and T. Kambe, \A testability analysis
method for register-transfer level descriptions," in Proc. Asia and South Pacic
Design Automation Conference, pp. 307{312, 1997.
[16] D. T. Wang, \An algorithm for the generation of test sets for combinational
logic network," IEEE Trans. Computers, pp. 742{746, July 1975.
[17] S.-J. Wang and T.-H. Yeh, \High-level test synthesis with hierarchical test
generation for delay-fault testability," IEEE Trans. Computer-Aided Design of
Integrated Circuits and Systems, pp. 1583{1596, Oct. 2009.
37