高速網路交換機之設計與實作｜國立清華大學博碩士論文庫

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研究生：	許育豪 Hsu, Yu-Hao
論文名稱：	高速網路交換機之設計與實作 The Design and Implementation of High-speed Network Switches
指導教授：	張正尚 Chang, Cheng-Shang 邱瀞德 Chiu, Ching-Te 吳仁銘 Wu, Jen-ming 徐碩鴻 Hsu, Shuo-Hung
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	118
中文關鍵詞：	網路交換機、效能百分百、可擴充性
外文關鍵詞：	Network Switch, 100% Throughput, Scability
相關次數：	點閱：1 下載：0
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由於近來光纖技術的發展，使得建立一個高速的網路交換機更顯得重要。現今市售的交換機都是建構在共享記憶體的基礎上，記憶體的存取速度便成了交換機系統的瓶頸，本篇論文乃設計與實現兩種突破性的交換機，以期能應用於未來光纖普及的高速網路。
第一種架構乃是基於本團隊所提出的負載平衡式布可夫－范紐曼交換機(Load Balanced Birkhoff-von Neumann Switch)。理論上已證明此架構可達效能百分百（100% throughput）的傳輸品質。此前瞻性架構的好處是來自於架構本身的可擴充性(scalability)，只要我們將4x4 埠的交換機實現，便能以此為單元建構出64x64、512x512 或更高埠的骨幹級交換器。本論文除了介紹核心的交換機數位電路，亦包含與外界溝通的類比SERDES (serializer-deserializer)介面，並介紹如何整合成混合性的系統晶片。最後並介紹此架構的第二代高速交換機晶片，說明如何將此交換機架構直接用射頻電路實現。
我們更進一步提出第二種架構：結合輸入及交叉點佇列交換機(Combinedinput and crosspoint queueing Switch)，提出使用動態方框演算法以期達到百分百效能下對數延遲（O(logN) delay）的可能性並且提供其理論驗證。此外，此種結合輸入及交叉點佇列交換機在單一傳送交通下每個交叉點只需要兩個封包大小的佇列。不同於輸入佇列交換機，動態方框演算法在多重傳送的交通設定下依舊可以達到效能百分百，而僅需增加每個交叉點的佇列大小。

There is an urgent need to built high speed switches that scale with the transmission speed of fiber optics. Most switches in the current market are based on the so-called shared memory switch architecture. As the speed of fiber optics advances, the memory access speed becomes a bottleneck.
A breakthrough in high-speed switch is the load balanced Birkhoff-von Neumann switch. It is proposed to resolve the memory access conflict and yield 100% throughput with high scalability. We implement the digital core of the load balanced switch in first, and then develop the analog SERDES interface to reduce the switch IC pin counts. The mixed-signal design of the switch system is then integrated
successfully. In the next generation, we also implement the switch IC directly in RF domain without the use of SERDES interfaces to achieve low propagation delay and high scalability.
We also propose the Combined Input and Crosspoint Queueing (CICQ) switch with the dynamic frame sizing algorithm for the possibility of O(logN) delay. It is formally shown that such the CICQ switch indeed achieves 100% throughput for certain Poisson-like traffic models. Moreover, such a CICQ switch only requires a two-cell buffer at each crosspoint when there is only unicast traffic. Unlike input-buffered switches, the dynamic frame sizing algorithm also achieves 100% throughput in the setting of multicast traffic. This is done at the cost of increasing the buffer size at each crosspoint.

Abstract ...............................I
摘要.................................. II
Acknowledgement...................... III
List of Contents.......................IV
List of Tables....................... VII
List of Figures.........................X
Chapter 1 Introduction................. 1
Chapter 2 Digital Core: A 20Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications........................... 5
2.1 Motivation......................... 5
2.2 An 8×8 Symmetric TDM Switch Module................................. 8
2.3 An 8×8 TDM Switch with 8/10B Codec IC.................................... 11
2.4 A Dual-Mode 8×8/64×64 Symmetric TDM Switch with High Speed Interfaces...................... 17
2.5 Summary........................... 19
Chapter 3 Analog Design: A Quarter-Rate 2.56/3.2Gbps 16/20:1 SERDES Interface in 0.18μm CMOS Technology............................ 20
3.1 Motivation........................ 20
3.2 Quarter-rate 1:16/20 Deserializer.......................... 22
3.3 Quarter-rate 16/20:1 Serializer............................ 25
3.4 Phase Lock Loop and CML I/O Interface............................. 28
3.5 Layout Schemes.................... 31
3.6 Experimental Results.............. 37
3.7 Summary........................... 40
Chapter 4 System Integration: A Scalable Folded Load Balanced Switch with SERDES Interface in 0.13μm CMOS Technology............................ 41
4.1 Motivation........................ 41
4.2 The Proposed Scalable LB-BvN STDM Switch Fabric................................ 45
4.3 The Implementation of the 4×4 LB-BvN STDM Switch Fabric.................................49
4.4 Experiment Results................ 61
4.5 Summary........................... 66
Chapter 5 A 32Gbps Low Propagation Delay 4×4 Switch IC for Feedback-Based System in 0.13μm CMOS Technology............................ 68
5.1 Motivation........................ 68
5.2 Circuits Design Techniques........ 71
5.3 Measurement Results............... 76
5.4 Summary........................... 79
Chapter 6 A Dynamic Frame Sizing Algorithm for CICQ Switches with 100% Throughput......... 80
6.1 Motivation........................ 80
6.2 Dynamic Frame Sizing Algorithms for Input buffered Switches ............................. 82
6.3 From Input-buffered Switches to CICQ Switches ............................. 90
6.4 CICQ Switches with Multicast Traffic............................... 95
6.5 Simulations ...................... 97
6.6 Summary........................... 98
6.6 Appendix ......................... 99
Chapter 7 Conclusion................. 103
References............................105
Vita..................................116

                                

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